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Stabilize Ratified RISC-V Target Features
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As shortly discussed on Zulip
(https://rust-lang.zulipchat.com/#narrow/stream/250483-t-compiler.2Frisc-v/topic/Stabilization.20of.20RISC-V.20Target.20Features/near/394793704), this commit stabilizes the ratified RISC-V instruction bases and extensions.

Specifically, this commit stabilizes the:
* Instruction-Fetch Fence (Zifencei) on v2.0
* Control and Status Register (Zcsr) on v2.0
* Pause Hint (Zihintpause) on v2.0
* Zicntr and Zihpm were ratified March 2023
* Total Store Ordering (Ztso) on v1.0
* Supervisor-level Instructions (S) on v1.12
* Atomic Instructions (A) on v2.0
* Compressed Instructions (C) on v2.0
* Double-Precision Floating-Point (D) on v2.2
* Embedded Base (E) (Given as `RV32E` / `RV64E`) on v2.0
* Single-Precision Floating-Point (F) on v2.2
* Integer Multiplication and Division (M) on v2.0
* Vector Operations (V) on v1.0
* Bit Manipulations (B) on v1.0 listed as `zba`, `zbc`, `zbs`
* Scalar Cryptography (Zk) v1.0.1 listed as `zk`, `zkn`, `zknd`, `zkne`, `zknh`, `zkr`, `zks`, `zksed`, `zksh`, `zkt`, `zbkb`, `zbkc` `zkbx`
* Double-Precision Floating-Point in Integer Register (Zdinx) on v1.0
* Half-Precision Floating-Point (Zfh) on v1.0
* Minimal Half-Precision Floating-Point (Zfhmin) on v1.0
* Single-Precision Floating-Point in Integer Register (Zfinx) on v1.0
* Half-Precision Floating-Point in Integer Register (Zhinx) on v1.0
* Minimal Half-Precision Floating-Point in Integer Register (Zhinxmin) on v1.0
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@coastalwhite
coastalwhite committed Oct 4, 2023
1 parent 333e9e9 commit fec1880
Showing 1 changed file with 40 additions and 41 deletions.
81 changes: 40 additions & 41 deletions crates/std_detect/src/detect/arch/riscv.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -99,65 +99,64 @@ features! {
/// * Zkt: `"zkt"`
///
/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
#[unstable(feature = "stdsimd", issue = "27731")]
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32i: "rv32i";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] rv32i: "rv32i";
/// RV32I Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zifencei: "zifencei";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zifencei: "zifencei";
/// "Zifencei" Instruction-Fetch Fence
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihintpause: "zihintpause";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zihintpause: "zihintpause";
/// "Zihintpause" Pause Hint
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv64i: "rv64i";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] rv64i: "rv64i";
/// RV64I Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] m: "m";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] m: "m";
/// "M" Standard Extension for Integer Multiplication and Division
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] a: "a";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] a: "a";
/// "A" Standard Extension for Atomic Instructions
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicsr: "zicsr";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zicsr: "zicsr";
/// "Zicsr", Control and Status Register (CSR) Instructions
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicntr: "zicntr";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zicntr: "zicntr";
/// "Zicntr", Standard Extension for Base Counters and Timers
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihpm: "zihpm";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zihpm: "zihpm";
/// "Zihpm", Standard Extension for Hardware Performance Counters
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] f: "f";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] f: "f";
/// "F" Standard Extension for Single-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] d: "d";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] d: "d";
/// "D" Standard Extension for Double-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] q: "q";
/// "Q" Standard Extension for Quad-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] c: "c";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] c: "c";
/// "C" Standard Extension for Compressed Instructions

@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfinx: "zfinx";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zfinx: "zfinx";
/// "Zfinx" Standard Extension for Single-Precision Floating-Point in Integer Registers
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zdinx: "zdinx";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zdinx: "zdinx";
/// "Zdinx" Standard Extension for Double-Precision Floating-Point in Integer Registers
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinx: "zhinx";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zhinx: "zhinx";
/// "Zhinx" Standard Extension for Half-Precision Floating-Point in Integer Registers
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinxmin: "zhinxmin";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zhinxmin: "zhinxmin";
/// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] ztso: "ztso";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] ztso: "ztso";
/// "Ztso" Standard Extension for Total Store Ordering

@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32e: "rv32e";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] rv32e: "rv32e";
/// RV32E Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv128i: "rv128i";
/// RV128I Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfh: "zfh";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zfh: "zfh";
/// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfhmin: "zfhmin";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zfhmin: "zfhmin";
/// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] b: "b";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] b: "b";
/// "B" Standard Extension for Bit Manipulation
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] j: "j";
/// "J" Standard Extension for Dynamically Translated Languages
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] p: "p";
/// "P" Standard Extension for Packed-SIMD Instructions
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] v: "v";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] v: "v";
/// "V" Standard Extension for Vector Operations
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zam: "zam";
/// "Zam" Standard Extension for Misaligned Atomics

@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] s: "s";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] s: "s";
/// Supervisor-Level ISA
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svnapot: "svnapot";
/// "Svnapot" Standard Extension for NAPOT Translation Contiguity
Expand All @@ -168,39 +167,39 @@ features! {
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] h: "h";
/// Hypervisor Extension

@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zba: "zba";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zba: "zba";
/// "Zba" Standard Extension for Address Generation Instructions
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbb: "zbb";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbb: "zbb";
/// "Zbb" Standard Extension for Basic Bit-Manipulation
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbc: "zbc";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbc: "zbc";
/// "Zbc" Standard Extension for Carry-less Multiplication
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbs: "zbs";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbs: "zbs";
/// "Zbs" Standard Extension for Single-Bit instructions

@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkb: "zbkb";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkb: "zbkb";
/// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkc: "zbkc";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkc: "zbkc";
/// "Zbkc" Standard Extension for Carry-less multiply instructions
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkx: "zbkx";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkx: "zbkx";
/// "Zbkx" Standard Extension for Crossbar permutation instructions
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknd: "zknd";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zknd: "zknd";
/// "Zknd" Standard Extension for NIST Suite: AES Decryption
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkne: "zkne";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkne: "zkne";
/// "Zkne" Standard Extension for NIST Suite: AES Encryption
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknh: "zknh";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zknh: "zknh";
/// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksed: "zksed";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zksed: "zksed";
/// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksh: "zksh";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zksh: "zksh";
/// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkr: "zkr";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkr: "zkr";
/// "Zkr" Standard Extension for Entropy Source Extension
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkn: "zkn";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkn: "zkn";
/// "Zkn" Standard Extension for NIST Algorithm Suite
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zks: "zks";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zks: "zks";
/// "Zks" Standard Extension for ShangMi Algorithm Suite
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zk: "zk";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zk: "zk";
/// "Zk" Standard Extension for Standard scalar cryptography extension
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkt: "zkt";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkt: "zkt";
/// "Zkt" Standard Extension for Data Independent Execution Latency
}

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