Commits on Jun 21, 2022

1. Re-enable atomic loads and stores for all RISC-V targets …

   This roughly reverts PR rust-lang#66548
   
   Atomic "CAS" are still disabled for targets without the
   *“A” Standard Extension for Atomic Instructions*.
   However this extension only adds instructions for operations more complex
   than simple loads and stores, which are always atomic when aligned.
   
   In the [Unprivileged Spec v. 20191213](https://riscv.org/technical/specifications/)
   section 2.6 *Load and Store Instructions* of
   chapter 2 *RV32I Base Integer Instruction Set* (emphasis mine):
   
   > Even when misaligned loads and stores complete successfully,
   > these accesses might run extremely slowly depending on the implementation
   > (e.g., when implemented via an invisible trap). Further-more, whereas
   > **naturally aligned loads and stores are guaranteed to execute atomically**,
   > misaligned loads and stores might not, and hence require
   > additional synchronization to ensure atomicity.
   
   Unfortunately PR rust-lang#66548 did not provide
   much details on the bug that motivated it, but
   rust-lang#66240 and
   rust-lang#85736 appear related
   and happen with targets that do have the A extension.

   

   SimonSapin committed Jun 21, 2022
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