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Fix invalid 128-bit division on 32-bit target (#41228) #41250

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merged 1 commit into from
Apr 13, 2017

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kennytm
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@kennytm kennytm commented Apr 12, 2017

The bug of #41228 is a typo, this line:

q = n.wrapping_shl(64u32.wrapping_sub(sr));

            // 1 <= sr <= u64::bits() - 1
            q = n.wrapping_shl(64u32.wrapping_sub(sr));

The 64 should be 128.

(Compare with https://github.com/rust-lang-nursery/compiler-builtins/blob/280d19f1127aa80739f4179152b11a5f7d36d79f/src/int/udiv.rs#L213-L214:

            // 1 <= sr <= <hty!($ty)>::bits() - 1
            q = n << (<$ty>::bits() - sr);

Or compare with the C implementation https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/udivmodti4.c#L113-L116

        /* 1 <= sr <= n_udword_bits - 1 */
        /* q.all = n.all << (n_utword_bits - sr); */
        q.s.low = 0;
        q.s.high = n.s.low << (n_udword_bits - sr);

)

Added a bunch of randomly generated division test cases to try to cover every described branch of udivmodti4.

…g#41228.

Added test cases to cover all special-cased branches of udivmodti4.
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Thanks for the pull request, and welcome! The Rust team is excited to review your changes, and you should hear from @nikomatsakis (or someone else) soon.

If any changes to this PR are deemed necessary, please add them as extra commits. This ensures that the reviewer can see what has changed since they last reviewed the code. Due to the way GitHub handles out-of-date commits, this should also make it reasonably obvious what issues have or haven't been addressed. Large or tricky changes may require several passes of review and changes.

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est31 commented Apr 12, 2017

Looks good. Thanks for the quick fix @kennytm!

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@bors r+

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bors commented Apr 12, 2017

📌 Commit 71a9e10 has been approved by nikomatsakis

@@ -180,7 +180,7 @@ pub mod reimpls {
sr = sr.wrapping_add(1);

// 1 <= sr <= u64::bits() - 1
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Actually, is the comment still correct?

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Yes, its consistent with the comment in the c implementation /* 1 <= sr <= n_udword_bits - 1 */.

Its types are defined here and here.

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And the C code is actually assuming it when executing the shift, it sets the low value to 0 because it knows that n gets shifted at least by 65 bits.

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@nikomatsakis The comment is about the range of sr, not the amount of shift, so it is still correct.

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bors commented Apr 13, 2017

⌛ Testing commit 71a9e10 with merge 9f151fd...

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bors commented Apr 13, 2017

💔 Test failed - status-appveyor

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TimNN commented Apr 13, 2017

frewsxcv added a commit to frewsxcv/rust that referenced this pull request Apr 13, 2017
Fix invalid 128-bit division on 32-bit target (rust-lang#41228)

The bug of rust-lang#41228 is a typo, this line: https://github.com/rust-lang/rust/blob/1dca19ae3fd195fa517e326a39bfee729da7cadb/src/libcompiler_builtins/lib.rs#L183

```rust
            // 1 <= sr <= u64::bits() - 1
            q = n.wrapping_shl(64u32.wrapping_sub(sr));
```

The **64** should be **128**.

(Compare with https://github.com/rust-lang-nursery/compiler-builtins/blob/280d19f1127aa80739f4179152b11a5f7d36d79f/src/int/udiv.rs#L213-L214:

```rust
            // 1 <= sr <= <hty!($ty)>::bits() - 1
            q = n << (<$ty>::bits() - sr);
```

Or compare with the C implementation https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/udivmodti4.c#L113-L116

```c
        /* 1 <= sr <= n_udword_bits - 1 */
        /* q.all = n.all << (n_utword_bits - sr); */
        q.s.low = 0;
        q.s.high = n.s.low << (n_udword_bits - sr);
```
)

Added a bunch of randomly generated division test cases to try to cover every described branch of `udivmodti4`.
frewsxcv added a commit to frewsxcv/rust that referenced this pull request Apr 13, 2017
Fix invalid 128-bit division on 32-bit target (rust-lang#41228)

The bug of rust-lang#41228 is a typo, this line: https://github.com/rust-lang/rust/blob/1dca19ae3fd195fa517e326a39bfee729da7cadb/src/libcompiler_builtins/lib.rs#L183

```rust
            // 1 <= sr <= u64::bits() - 1
            q = n.wrapping_shl(64u32.wrapping_sub(sr));
```

The **64** should be **128**.

(Compare with https://github.com/rust-lang-nursery/compiler-builtins/blob/280d19f1127aa80739f4179152b11a5f7d36d79f/src/int/udiv.rs#L213-L214:

```rust
            // 1 <= sr <= <hty!($ty)>::bits() - 1
            q = n << (<$ty>::bits() - sr);
```

Or compare with the C implementation https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/udivmodti4.c#L113-L116

```c
        /* 1 <= sr <= n_udword_bits - 1 */
        /* q.all = n.all << (n_utword_bits - sr); */
        q.s.low = 0;
        q.s.high = n.s.low << (n_udword_bits - sr);
```
)

Added a bunch of randomly generated division test cases to try to cover every described branch of `udivmodti4`.
frewsxcv added a commit to frewsxcv/rust that referenced this pull request Apr 13, 2017
Fix invalid 128-bit division on 32-bit target (rust-lang#41228)

The bug of rust-lang#41228 is a typo, this line: https://github.com/rust-lang/rust/blob/1dca19ae3fd195fa517e326a39bfee729da7cadb/src/libcompiler_builtins/lib.rs#L183

```rust
            // 1 <= sr <= u64::bits() - 1
            q = n.wrapping_shl(64u32.wrapping_sub(sr));
```

The **64** should be **128**.

(Compare with https://github.com/rust-lang-nursery/compiler-builtins/blob/280d19f1127aa80739f4179152b11a5f7d36d79f/src/int/udiv.rs#L213-L214:

```rust
            // 1 <= sr <= <hty!($ty)>::bits() - 1
            q = n << (<$ty>::bits() - sr);
```

Or compare with the C implementation https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/udivmodti4.c#L113-L116

```c
        /* 1 <= sr <= n_udword_bits - 1 */
        /* q.all = n.all << (n_utword_bits - sr); */
        q.s.low = 0;
        q.s.high = n.s.low << (n_udword_bits - sr);
```
)

Added a bunch of randomly generated division test cases to try to cover every described branch of `udivmodti4`.
bors added a commit that referenced this pull request Apr 13, 2017
Rollup of 3 pull requests

- Successful merges: #41240, #41250, #41266
- Failed merges:
@bors bors merged commit 71a9e10 into rust-lang:master Apr 13, 2017
@kennytm kennytm deleted the fix-41228 branch April 17, 2017 15:37
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6 participants