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Inline ASM: Registers in the dreg_low16 register class fail cause compilation failures when the d32 target feature is disabled #126797

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beetrees opened this issue Jun 21, 2024 · 1 comment · Fixed by #126849
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A-inline-assembly Area: Inline assembly (`asm!(…)`) C-bug Category: This is a bug. O-Arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state

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@beetrees
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I tried this code, compiled for the armv7-unknown-linux-gnueabihf target:

// Fails to compile
fn f(x: f64) {
    unsafe {
        let out: f64;
        std::arch::asm!("vmov.f64 d1, d0", out("d1") out, in("d0") x);
    }
}

I expected to see this happen: Successful compilation, as the following code successfully compiles, and d0 and d1 are members of the dreg_low16 register class:

// Successfully compiles
fn f(x: f64) {
    unsafe {
        let out: f64;
        std::arch::asm!("vmov.f64 {}, {}", out(dreg_low16) out, in(dreg_low16) x);
    }
}

Instead, this happened: Compilation fails with the following error message:

error: register class `dreg` requires the `d32` target feature
 --> <source>:5:44
  |
5 |         std::arch::asm!("vmov.f64 d1, d0", out("d1") out, in("d0") x);
  |                                            ^^^^^^^^^^^^^

error: register class `dreg` requires the `d32` target feature
 --> <source>:5:59
  |
5 |         std::arch::asm!("vmov.f64 d1, d0", out("d1") out, in("d0") x);
  |                                                           ^^^^^^^^^^

error: aborting due to 2 previous errors

Meta

rustc --version --verbose:

rustc 1.81.0-nightly (d8a38b000 2024-06-19)
binary: rustc
commit-hash: d8a38b00024cd7156dea4ce8fd8ae113a2745e7f
commit-date: 2024-06-19
host: x86_64-unknown-linux-gnu
release: 1.81.0-nightly
LLVM version: 18.1.7
@beetrees beetrees added the C-bug Category: This is a bug. label Jun 21, 2024
@rustbot rustbot added the needs-triage This issue may need triage. Remove it if it has been sufficiently triaged. label Jun 21, 2024
@beetrees
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@rustbot label +A-inline-assembly +O-Arm

@rustbot rustbot added A-inline-assembly Area: Inline assembly (`asm!(…)`) O-Arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state labels Jun 21, 2024
workingjubilee added a commit to workingjubilee/rustc that referenced this issue Jun 24, 2024
…arm-low-dregs, r=Amanieu

Fix 32-bit Arm reg classes by hierarchically sorting them

We were rejecting legal `asm!` because we were asking for the "greatest" feature that includes a register class, instead of the "least" feature that includes a register class. This was only revealed on certain 32-bit Arm targets because not all have the same register limitations.

This is a somewhat hacky solution, but other solutions would require potentially rearchitecting how the internals of parsing or rejecting register classes work for all targets.

Fixes rust-lang#126797

r​? `@Amanieu`
@bors bors closed this as completed in 3108dfa Jun 24, 2024
rust-timer added a commit to rust-lang-ci/rust that referenced this issue Jun 24, 2024
Rollup merge of rust-lang#126849 - workingjubilee:correctly-classify-arm-low-dregs, r=Amanieu

Fix 32-bit Arm reg classes by hierarchically sorting them

We were rejecting legal `asm!` because we were asking for the "greatest" feature that includes a register class, instead of the "least" feature that includes a register class. This was only revealed on certain 32-bit Arm targets because not all have the same register limitations.

This is a somewhat hacky solution, but other solutions would require potentially rearchitecting how the internals of parsing or rejecting register classes work for all targets.

Fixes rust-lang#126797

r​? ``@Amanieu``
@saethlin saethlin removed the needs-triage This issue may need triage. Remove it if it has been sufficiently triaged. label Jun 29, 2024
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Labels
A-inline-assembly Area: Inline assembly (`asm!(…)`) C-bug Category: This is a bug. O-Arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state
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3 participants