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Tracking Issue for RISC-V Ratified Extensions Intrinsics #114544
Labels
A-floating-point
Area: Floating point numbers and arithmetic
A-SIMD
Area: SIMD (Single Instruction Multiple Data)
A-target-feature
Area: Enabling/disabling target features like AVX, Neon, etc.
C-tracking-issue
Category: An issue tracking the progress of sth. like the implementation of an RFC
O-riscv
Target: RISC-V architecture
T-libs-api
Relevant to the library API team, which will review and decide on the PR/issue.
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coastalwhite
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C-tracking-issue
Category: An issue tracking the progress of sth. like the implementation of an RFC
T-libs-api
Relevant to the library API team, which will review and decide on the PR/issue.
labels
Aug 6, 2023
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This was referenced Aug 6, 2023
Two additional points:
|
Entropy Source of the Cryptographic Scalar Extension are not implemented in LLVM. Therefore, it should be implemented with inline assembly and is not part of the implemented intrinsics. |
Extensions such as |
This was referenced Sep 30, 2023
This was referenced Oct 26, 2023
bors
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Oct 30, 2023
…features, r=Amanieu Stabilize Ratified RISC-V Target Features Stabilization PR for the ratified RISC-V target features. This stabilizes some of the target features tracked by rust-lang#44839. This is also a part of rust-lang#114544 and eventually needed for the RISC-V part of rust-lang/rfcs#3268. There is a similar PR for the the stdarch crate which can be found at rust-lang/stdarch#1476. This was briefly discussed on Zulip (https://rust-lang.zulipchat.com/#narrow/stream/250483-t-compiler.2Frisc-v/topic/Stabilization.20of.20RISC-V.20Target.20Features/near/394793704). Specifically, this PR stabilizes the: * Atomic Instructions (A) on v2.0 * Compressed Instructions (C) on v2.0 * ~Double-Precision Floating-Point (D) on v2.2~ * ~Embedded Base (E) (Given as `RV32E` / `RV64E`) on v2.0~ * ~Single-Precision Floating-Point (F) on v2.2~ * Integer Multiplication and Division (M) on v2.0 * ~Vector Operations (V) on v1.0~ * Bit Manipulations (B) on v1.0 listed as `zba`, `zbc`, `zbs` * Scalar Cryptography (Zk) v1.0.1 listed as `zk`, `zkn`, `zknd`, `zkne`, `zknh`, `zkr`, `zks`, `zksed`, `zksh`, `zkt`, `zbkb`, `zbkc` `zkbx` * ~Double-Precision Floating-Point in Integer Register (Zdinx) on v1.0~ * ~Half-Precision Floating-Point (Zfh) on v1.0~ * ~Minimal Half-Precision Floating-Point (Zfhmin) on v1.0~ * ~Single-Precision Floating-Point in Integer Register (Zfinx) on v1.0~ * ~Half-Precision Floating-Point in Integer Register (Zhinx) on v1.0~ * ~Minimal Half-Precision Floating-Point in Integer Register (Zhinxmin) on v1.0~ r? `@Amanieu`
endeneer
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Nov 30, 2023
This commit is to solve the following build error: ``` error[E0658]: use of unstable library feature 'riscv_ext_intrinsics' --> src/guest/vmexit.rs:236:9 | 236 | core::arch::riscv64::hfence_gvma_all(); | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | = note: see issue #114544 <rust-lang/rust#114544> for more information = help: add `#![feature(riscv_ext_intrinsics)]` to the crate attributes to enable ``` Signed-off-by: Tan En De <ende.tan@starfivetech.com>
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workingjubilee
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O-riscv
Target: RISC-V architecture
A-floating-point
Area: Floating point numbers and arithmetic
A-SIMD
Area: SIMD (Single Instruction Multiple Data)
A-target-feature
Area: Enabling/disabling target features like AVX, Neon, etc.
labels
Nov 5, 2024
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Labels
A-floating-point
Area: Floating point numbers and arithmetic
A-SIMD
Area: SIMD (Single Instruction Multiple Data)
A-target-feature
Area: Enabling/disabling target features like AVX, Neon, etc.
C-tracking-issue
Category: An issue tracking the progress of sth. like the implementation of an RFC
O-riscv
Target: RISC-V architecture
T-libs-api
Relevant to the library API team, which will review and decide on the PR/issue.
This issue tracks the implementation of all the intrinsics linked to the Ratified RISC-V Extensions. The, not yet stable intrinsics are behind the
riscv_ext_intrinsics
nightly feature.Steps
stdarch
Zkr
. Entropy source extensionHalf-PrecisionFloat in IntegerUnresolved Questions
How to deal with instructions that are already dealt with by LLVM intrinsics and library features (e.g.cpop
andu*::count_ones
)? Include them or not?usize
for riscv32 orriscv64
specific intrinsics or useu32
andu64
respectively?How to deal with intrinsics involving immediate values?Use theasm_const
feature outlined in Tracking Issue for asm_const #93332.Use the trick described in Implement all x86 vendor intrinsics stdarch#40 and illustrated in_mm_cmpestri
.Implementation History
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