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Switch "native" check from being x86_64 only to checking HOST #369

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Merged
merged 2 commits into from
Dec 29, 2021
Merged

Switch "native" check from being x86_64 only to checking HOST #369

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f0dc654
Switch "native" check from being x86_64 only to checking `HOST`
TDHolmes Dec 15, 2021
dcc53bf
re-enable has_fpu
TDHolmes Dec 17, 2021
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5 changes: 5 additions & 0 deletions build.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -3,9 +3,14 @@ use std::{env, fs};

fn main() {
let target = env::var("TARGET").unwrap();
let host_triple = env::var("HOST").unwrap();
let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
let name = env::var("CARGO_PKG_NAME").unwrap();

if host_triple == target {
println!("cargo:rustc-cfg=native");
}

if target.starts_with("thumb") {
let suffix = if env::var_os("CARGO_FEATURE_LINKER_PLUGIN_LTO").is_some() {
"-lto"
Expand Down
6 changes: 3 additions & 3 deletions src/peripheral/icb.rs
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@@ -1,6 +1,6 @@
//! Implementation Control Block

#[cfg(any(armv7m, armv8m, target_arch = "x86_64"))]
#[cfg(any(armv7m, armv8m, native))]
use volatile_register::RO;
use volatile_register::RW;

Expand All @@ -12,12 +12,12 @@ pub struct RegisterBlock {
/// The bottom four bits of this register give the number of implemented
/// interrupt lines, divided by 32. So a value of `0b0010` indicates 64
/// interrupts.
#[cfg(any(armv7m, armv8m, target_arch = "x86_64"))]
#[cfg(any(armv7m, armv8m, native))]
pub ictr: RO<u32>,

/// The ICTR is not defined in the ARMv6-M Architecture Reference manual, so
/// we replace it with this.
#[cfg(not(any(armv7m, armv8m, target_arch = "x86_64")))]
#[cfg(not(any(armv7m, armv8m, native)))]
_reserved: u32,

/// Auxiliary Control Register
Expand Down
8 changes: 4 additions & 4 deletions src/peripheral/mod.rs
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Expand Up @@ -71,8 +71,8 @@ pub mod dcb;
pub mod dwt;
#[cfg(not(armv6m))]
pub mod fpb;
// NOTE(target_arch) is for documentation purposes
#[cfg(any(has_fpu, target_arch = "x86_64"))]
// NOTE(native) is for documentation purposes
#[cfg(any(has_fpu, native))]
pub mod fpu;
pub mod icb;
#[cfg(all(not(armv6m), not(armv8m_base)))]
Expand Down Expand Up @@ -411,7 +411,7 @@ pub struct FPU {

unsafe impl Send for FPU {}

#[cfg(any(has_fpu, target_arch = "x86_64"))]
#[cfg(any(has_fpu, native))]
impl FPU {
/// Pointer to the register block
pub const PTR: *const fpu::RegisterBlock = 0xE000_EF30 as *const _;
Expand All @@ -423,7 +423,7 @@ impl FPU {
}
}

#[cfg(any(has_fpu, target_arch = "x86_64"))]
#[cfg(any(has_fpu, native))]
impl ops::Deref for FPU {
type Target = self::fpu::RegisterBlock;

Expand Down
10 changes: 5 additions & 5 deletions src/peripheral/scb.rs
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Expand Up @@ -182,7 +182,7 @@ impl SCB {
5 => VectActive::Exception(Exception::BusFault),
#[cfg(not(armv6m))]
6 => VectActive::Exception(Exception::UsageFault),
#[cfg(any(armv8m, target_arch = "x86_64"))]
#[cfg(any(armv8m, native))]
7 => VectActive::Exception(Exception::SecureFault),
11 => VectActive::Exception(Exception::SVCall),
#[cfg(not(armv6m))]
Expand Down Expand Up @@ -218,7 +218,7 @@ pub enum Exception {
UsageFault,

/// Secure fault interrupt (only on ARMv8-M)
#[cfg(any(armv8m, target_arch = "x86_64"))]
#[cfg(any(armv8m, native))]
SecureFault,

/// SV call interrupt
Expand Down Expand Up @@ -250,7 +250,7 @@ impl Exception {
Exception::BusFault => -11,
#[cfg(not(armv6m))]
Exception::UsageFault => -10,
#[cfg(any(armv8m, target_arch = "x86_64"))]
#[cfg(any(armv8m, native))]
Exception::SecureFault => -9,
Exception::SVCall => -5,
#[cfg(not(armv6m))]
Expand Down Expand Up @@ -293,7 +293,7 @@ impl VectActive {
5 => VectActive::Exception(Exception::BusFault),
#[cfg(not(armv6m))]
6 => VectActive::Exception(Exception::UsageFault),
#[cfg(any(armv8m, target_arch = "x86_64"))]
#[cfg(any(armv8m, native))]
7 => VectActive::Exception(Exception::SecureFault),
11 => VectActive::Exception(Exception::SVCall),
#[cfg(not(armv6m))]
Expand Down Expand Up @@ -934,7 +934,7 @@ pub enum SystemHandler {
UsageFault = 6,

/// Secure fault interrupt (only on ARMv8-M)
#[cfg(any(armv8m, target_arch = "x86_64"))]
#[cfg(any(armv8m, native))]
SecureFault = 7,

/// SV call interrupt
Expand Down