Reduce the range of vreg voltage to be on-target-test

rp-rs · Feb 25, 2024 · 6263bfc · 6263bfc
1 parent 7d8a8c2
commit 6263bfc
Showing 1 changed file with 8 additions and 26 deletions.
diff --git a/on-target-tests/tests/vreg_change_voltage.rs b/on-target-tests/tests/vreg_change_voltage.rs
@@ -62,44 +62,26 @@ mod tests {
 
     #[test]
     fn change_onchip_regulator_voltage(state: &mut State) {
-        // Set the voltage to 1.20V
-        let target_voltage = VSEL_A::VOLTAGE1_20;
-        vreg::set_voltage(&mut state.vreg, target_voltage);
-        let v = vreg::get_voltage(&mut state.vreg).unwrap();
-        assert!(v == target_voltage);
-
-        // Set the voltage to 1.25V
-        let target_voltage = VSEL_A::VOLTAGE1_25;
-        vreg::set_voltage(&mut state.vreg, target_voltage);
-        let v = vreg::get_voltage(&mut state.vreg).unwrap();
-        assert!(v == target_voltage);
-
-        // Set the voltage to 1.30V
-        let target_voltage = VSEL_A::VOLTAGE1_30;
-        vreg::set_voltage(&mut state.vreg, target_voltage);
-        let v = vreg::get_voltage(&mut state.vreg).unwrap();
-        assert!(v == target_voltage);
-
-        // Set the voltage to 0.90V
-        let target_voltage = VSEL_A::VOLTAGE0_90;
+        // Set the voltage to 1.05V
+        let target_voltage = VSEL_A::VOLTAGE1_05;
         vreg::set_voltage(&mut state.vreg, target_voltage);
         let v = vreg::get_voltage(&mut state.vreg).unwrap();
         assert!(v == target_voltage);
 
-        // Set the voltage to 0.95V
-        let target_voltage = VSEL_A::VOLTAGE0_95;
+        // Set the voltage to 1.10V
+        let target_voltage = VSEL_A::VOLTAGE1_10;
         vreg::set_voltage(&mut state.vreg, target_voltage);
         let v = vreg::get_voltage(&mut state.vreg).unwrap();
         assert!(v == target_voltage);
 
-        // Set the voltage to 1.00V
-        let target_voltage = VSEL_A::VOLTAGE1_00;
+        // Set the voltage to 1.15V
+        let target_voltage = VSEL_A::VOLTAGE1_15;
         vreg::set_voltage(&mut state.vreg, target_voltage);
         let v = vreg::get_voltage(&mut state.vreg).unwrap();
         assert!(v == target_voltage);
 
-        // Set the voltage to 1.05V
-        let target_voltage = VSEL_A::VOLTAGE1_05;
+        // Set the voltage to 1.20V
+        let target_voltage = VSEL_A::VOLTAGE1_20;
         vreg::set_voltage(&mut state.vreg, target_voltage);
         let v = vreg::get_voltage(&mut state.vreg).unwrap();
         assert!(v == target_voltage);