Release v2.1 (RV32IMAC_Zicsr_Zifencei)

This release adds:

• Optional user privilege mode
• PMP (memory protection) with configurable granularity
• mtval support for access violations and illegal instructions
• More pipelining options

With most of the CPU features finished to my satisfaction, the next steps will involve more software and a GPU ;)

Release v2.0.1 (RV32IMAC_Zicsr_Zifencei)

The CPU didn't really change but I forgot to remove testing code from the bootloader :P

Release 2.0 (RV32IMAC_Zicsr_Zifencei)

This release adds:

• Instruction sets configurable with parameters
• Optional writeability to the misa CSR
• The A (atomic memory operations) extension
• A new external interface for atomics

Because the presence of the A extension requires additional external logic, instead of just some signals that can be ignored, the semver MAJOR number was incremented, resulting in v2.0.
This feature marks the completion of my initial goals and the last instruction set I will implement for the time being.

Release v1.3 (RV32IMC_Zicsr_Zifencei)

This release adds support for memory-ordering instructions, with FENCE now producing outputs that indicate acquire and release fences and FENCE.I producing an output indicating an instruction fetch fence and clearing the pipeline.

Release v1.2.1 (RV32IMC_Zicsr)

This release adds the marchid value 37 after it was allocated by RISC-V in the open-source marchid list.
It is otherwise identical to release v1.2.

Release v1.2 (RV32IMC_Zicsr)

This release fixes:

• An issue where the IF stage locks up after exiting reset
• An issue that caused forwarding logic to fail under very specific circumstances
• The mtime interrupt was erroneously assigned number 3, not 7
• The divider only worked for a latency of 1

Boa keeps becoming more stable, hopefully I don't find any more well-hidden bugs :P

Release v1.1 (RV32IMC_Zicsr)

This release fixes a major instruction decoding bug that caused the WFI instruction to be considered illegal.
It also fixes circular combinatorial in the forwarding logic.

Release v1.0 (RV32IMC_Zicsr)

Boa32 now passes all relevant RISC-V unit tests and I'm satisfied that it is now a fully compliant RISC-V core.