librz/arch: sync with latest LLVM Hexagon v79 version. (#4923)

* Sync with latest LLVM Hexagon v79 version. This uses llvm/llvm-project#120983 which is imcomplete (apparently it misses some HVX instructions). But it replaced some imported instructions with the LLVM definitions. * Add newly generate il operations.
rizinorg · Feb 22, 2025 · efbab1d · efbab1d
1 parent cc97951
commit efbab1d
Show file tree

Hide file tree

Showing 40 changed files with 173 additions and 173 deletions.
diff --git a/librz/arch/isa/hexagon/hexagon_disas.c b/librz/arch/isa/hexagon/hexagon_disas.c
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-21 18:11:59-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:
@@ -21216,6 +21216,20 @@ static const HexInsnTemplate templates_normal_0x9[] = {
 		.type = RZ_ANALYSIS_OP_TYPE_NULL,
 		.syntax = " = memuh(<<+)",
 	},
+	{
+		// 10010010000sssssPP1ttttt000ddddd | Rd = memw_phys(Rs,Rt)
+		.encoding = { .mask = 0xffe020e0, .op = 0x92002000 },
+		.id = HEX_INS_L4_LOADW_PHYS,
+		.ops = {
+			{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 'd', .syntax = 0 },
+			{ .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 's', .syntax = 13 },
+			{ .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 't', .syntax = 14 },
+		},
+		.pred = HEX_NOPRED,
+		.cond = RZ_TYPE_COND_AL,
+		.type = RZ_ANALYSIS_OP_TYPE_NULL,
+		.syntax = " = memw_phys(,)",
+	},
 	{
 		// 10011111000iiiiiPP101tti100ddddd | if (!Pt) Rd = memb(Ii)
 		.encoding = { .mask = 0xffe038e0, .op = 0x9f002880 },
@@ -21720,20 +21734,6 @@ static const HexInsnTemplate templates_normal_0x9[] = {
 		.type = RZ_ANALYSIS_OP_TYPE_NULL,
 		.syntax = "dcfetch(+)",
 	},
-	{
-		// 10010010000sssssPP1ttttt000ddddd | Rd = memw_phys(Rs,Rt)
-		.encoding = { .mask = 0xffe020e0, .op = 0x92002000 },
-		.id = HEX_INS_IMPORTED_RD_MEMW_PHYS_RS_RT,
-		.ops = {
-			{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 'd', .syntax = 0 },
-			{ .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 's', .syntax = 13 },
-			{ .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 't', .syntax = 14 },
-		},
-		.pred = HEX_NOPRED,
-		.cond = RZ_TYPE_COND_AL,
-		.type = RZ_ANALYSIS_OP_TYPE_NULL,
-		.syntax = " = memw_phys(,)",
-	},
 	{ { 0 } },
 };
 
@@ -24119,28 +24119,28 @@ static const HexInsnTemplate templates_normal_0xa[] = {
 		.syntax = " = dmwait",
 	},
 	{
-		// 1010011010100000PP0ttttt00000000 | l2gclean(Rtt)
-		.encoding = { .mask = 0xffff20ff, .op = 0xa6a00000 },
-		.id = HEX_INS_IMPORTED_L2GCLEAN_RTT,
+		// 1010011011000000PP0ttttt00000000 | l2gcleaninv(Rtt)
+		.encoding = { .mask = 0xffff20ff, .op = 0xa6c00000 },
+		.id = HEX_INS_Y6_L2GCLEANINVPA,
 		.ops = {
-			{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .isa_id = 't', .syntax = 9 },
+			{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .isa_id = 't', .syntax = 12 },
 		},
 		.pred = HEX_NOPRED,
 		.cond = RZ_TYPE_COND_AL,
 		.type = RZ_ANALYSIS_OP_TYPE_NULL,
-		.syntax = "l2gclean()",
+		.syntax = "l2gcleaninv()",
 	},
 	{
-		// 1010011011000000PP0ttttt00000000 | l2gcleaninv(Rtt)
-		.encoding = { .mask = 0xffff20ff, .op = 0xa6c00000 },
-		.id = HEX_INS_IMPORTED_L2GCLEANINV_RTT,
+		// 1010011010100000PP0ttttt00000000 | l2gclean(Rtt)
+		.encoding = { .mask = 0xffff20ff, .op = 0xa6a00000 },
+		.id = HEX_INS_Y6_L2GCLEANPA,
 		.ops = {
-			{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .isa_id = 't', .syntax = 12 },
+			{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .isa_id = 't', .syntax = 9 },
 		},
 		.pred = HEX_NOPRED,
 		.cond = RZ_TYPE_COND_AL,
 		.type = RZ_ANALYSIS_OP_TYPE_NULL,
-		.syntax = "l2gcleaninv()",
+		.syntax = "l2gclean()",
 	},
 	{ { 0 } },
 };

diff --git a/librz/arch/isa/hexagon/hexagon_il.h b/librz/arch/isa/hexagon/hexagon_il.h
@@ -879,6 +879,7 @@ RzILOpEffect *hex_il_op_l4_loadrub_ur(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_l4_loadruh_ap(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_l4_loadruh_rr(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_l4_loadruh_ur(HexInsnPktBundle *bundle);
+RzILOpEffect *hex_il_op_l4_loadw_phys(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_l4_or_memopb_io(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_l4_or_memoph_io(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_l4_or_memopw_io(HexInsnPktBundle *bundle);
@@ -2021,17 +2022,16 @@ RzILOpEffect *hex_il_op_y6_dmpoll(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_y6_dmresume(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_y6_dmstart(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_y6_dmwait(HexInsnPktBundle *bundle);
+RzILOpEffect *hex_il_op_y6_l2gcleaninvpa(HexInsnPktBundle *bundle);
+RzILOpEffect *hex_il_op_y6_l2gcleanpa(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_dep_a2_addsat(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_dep_a2_subsat(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_dep_s2_packhl(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_invalid_decode(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_imported_rd_ss(HexInsnPktBundle *bundle);
-RzILOpEffect *hex_il_op_imported_rd_memw_phys_rs_rt(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_imported_rdd_sss(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_imported_sd_rs(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_imported_sdd_rss(HexInsnPktBundle *bundle);
-RzILOpEffect *hex_il_op_imported_l2gclean_rtt(HexInsnPktBundle *bundle);
-RzILOpEffect *hex_il_op_imported_l2gcleaninv_rtt(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_sa1_addi(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_sa1_addrx(HexInsnPktBundle *bundle);
 RzILOpEffect *hex_il_op_sa1_addsp(HexInsnPktBundle *bundle);

diff --git a/librz/arch/isa/hexagon/hexagon_il_getter_table.h b/librz/arch/isa/hexagon/hexagon_il_getter_table.h
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-22 07:05:24-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:
@@ -1199,9 +1199,6 @@ static HexILInsn hex_il_getter_lt[] = {
 	{ { (HexILOpGetter)hex_il_op_imported_rd_ss, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
-	{ { (HexILOpGetter)hex_il_op_imported_rd_memw_phys_rs_rt, HEX_IL_INSN_ATTR_INVALID },
-		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
-		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
 	{ { (HexILOpGetter)hex_il_op_imported_rdd_sss, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
@@ -1211,12 +1208,6 @@ static HexILInsn hex_il_getter_lt[] = {
 	{ { (HexILOpGetter)hex_il_op_imported_sdd_rss, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
-	{ { (HexILOpGetter)hex_il_op_imported_l2gclean_rtt, HEX_IL_INSN_ATTR_INVALID },
-		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
-		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
-	{ { (HexILOpGetter)hex_il_op_imported_l2gcleaninv_rtt, HEX_IL_INSN_ATTR_INVALID },
-		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
-		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
 	{ { (HexILOpGetter)hex_il_op_j2_call, HEX_IL_INSN_ATTR_BRANCH },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
@@ -2258,6 +2249,9 @@ static HexILInsn hex_il_getter_lt[] = {
 	{ { (HexILOpGetter)hex_il_op_l4_loadruh_ur, HEX_IL_INSN_ATTR_MEM_READ },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
+	{ { (HexILOpGetter)hex_il_op_l4_loadw_phys, HEX_IL_INSN_ATTR_INVALID },
+		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
+		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
 	{ { (HexILOpGetter)hex_il_op_l4_or_memopb_io, HEX_IL_INSN_ATTR_MEM_WRITE | HEX_IL_INSN_ATTR_MEM_READ },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
@@ -6705,6 +6699,12 @@ static HexILInsn hex_il_getter_lt[] = {
 	{ { (HexILOpGetter)hex_il_op_y6_dmwait, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
+	{ { (HexILOpGetter)hex_il_op_y6_l2gcleaninvpa, HEX_IL_INSN_ATTR_INVALID },
+		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
+		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
+	{ { (HexILOpGetter)hex_il_op_y6_l2gcleanpa, HEX_IL_INSN_ATTR_INVALID },
+		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
+		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
 	{ { (HexILOpGetter)hex_il_op_dep_a2_addsat, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
 		{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },

diff --git a/librz/arch/isa/hexagon/hexagon_insn.h b/librz/arch/isa/hexagon/hexagon_insn.h
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-21 18:11:59-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:
@@ -407,12 +407,9 @@ typedef enum {
 	HEX_INS_G4_TFRGPCP,
 	HEX_INS_G4_TFRGRCR,
 	HEX_INS_IMPORTED_RD_SS,
-	HEX_INS_IMPORTED_RD_MEMW_PHYS_RS_RT,
 	HEX_INS_IMPORTED_RDD_SSS,
 	HEX_INS_IMPORTED_SD_RS,
 	HEX_INS_IMPORTED_SDD_RSS,
-	HEX_INS_IMPORTED_L2GCLEAN_RTT,
-	HEX_INS_IMPORTED_L2GCLEANINV_RTT,
 	HEX_INS_J2_CALL,
 	HEX_INS_J2_CALLF,
 	HEX_INS_J2_CALLR,
@@ -760,6 +757,7 @@ typedef enum {
 	HEX_INS_L4_LOADRUH_AP,
 	HEX_INS_L4_LOADRUH_RR,
 	HEX_INS_L4_LOADRUH_UR,
+	HEX_INS_L4_LOADW_PHYS,
 	HEX_INS_L4_OR_MEMOPB_IO,
 	HEX_INS_L4_OR_MEMOPH_IO,
 	HEX_INS_L4_OR_MEMOPW_IO,
@@ -2386,8 +2384,10 @@ typedef enum {
 	HEX_INS_Y6_DMRESUME,
 	HEX_INS_Y6_DMSTART,
 	HEX_INS_Y6_DMWAIT,
+	HEX_INS_Y6_L2GCLEANINVPA,
+	HEX_INS_Y6_L2GCLEANPA,
 	HEX_INS_DEP_A2_ADDSAT,
 	HEX_INS_DEP_A2_SUBSAT,
 	HEX_INS_DEP_S2_PACKHL,
 } HexInsnID;
-#endif
+#endif
diff --git a/librz/arch/isa/hexagon/il_ops/hexagon_il_A6_ops.c b/librz/arch/isa/hexagon/il_ops/hexagon_il_A6_ops.c
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-22 07:05:24-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

diff --git a/librz/arch/isa/hexagon/il_ops/hexagon_il_A7_ops.c b/librz/arch/isa/hexagon/il_ops/hexagon_il_A7_ops.c
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-22 07:05:24-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

diff --git a/librz/arch/isa/hexagon/il_ops/hexagon_il_C2_ops.c b/librz/arch/isa/hexagon/il_ops/hexagon_il_C2_ops.c
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-22 07:05:24-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

diff --git a/librz/arch/isa/hexagon/il_ops/hexagon_il_C4_ops.c b/librz/arch/isa/hexagon/il_ops/hexagon_il_C4_ops.c
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-22 07:05:24-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

diff --git a/librz/arch/isa/hexagon/il_ops/hexagon_il_F2_ops.c b/librz/arch/isa/hexagon/il_ops/hexagon_il_F2_ops.c
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-22 07:05:24-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

diff --git a/librz/arch/isa/hexagon/il_ops/hexagon_il_G4_ops.c b/librz/arch/isa/hexagon/il_ops/hexagon_il_G4_ops.c
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-22 07:05:24-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

diff --git a/librz/arch/isa/hexagon/il_ops/hexagon_il_IMPORTED_ops.c b/librz/arch/isa/hexagon/il_ops/hexagon_il_IMPORTED_ops.c
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-22 07:05:24-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:
@@ -19,11 +19,6 @@ RzILOpEffect *hex_il_op_imported_rd_ss(HexInsnPktBundle *bundle) {
 	NOT_IMPLEMENTED;
 }
 
-// Rd = memw_phys(Rs,Rt)
-RzILOpEffect *hex_il_op_imported_rd_memw_phys_rs_rt(HexInsnPktBundle *bundle) {
-	NOT_IMPLEMENTED;
-}
-
 // Rdd = Sss
 RzILOpEffect *hex_il_op_imported_rdd_sss(HexInsnPktBundle *bundle) {
 	NOT_IMPLEMENTED;
@@ -39,14 +34,4 @@ RzILOpEffect *hex_il_op_imported_sdd_rss(HexInsnPktBundle *bundle) {
 	NOT_IMPLEMENTED;
 }
 
-// l2gclean(Rtt)
-RzILOpEffect *hex_il_op_imported_l2gclean_rtt(HexInsnPktBundle *bundle) {
-	NOT_IMPLEMENTED;
-}
-
-// l2gcleaninv(Rtt)
-RzILOpEffect *hex_il_op_imported_l2gcleaninv_rtt(HexInsnPktBundle *bundle) {
-	NOT_IMPLEMENTED;
-}
-
 #include <rz_il/rz_il_opbuilder_end.h>
diff --git a/librz/arch/isa/hexagon/il_ops/hexagon_il_J2_ops.c b/librz/arch/isa/hexagon/il_ops/hexagon_il_J2_ops.c
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-22 07:05:24-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

diff --git a/librz/arch/isa/hexagon/il_ops/hexagon_il_J4_ops.c b/librz/arch/isa/hexagon/il_ops/hexagon_il_J4_ops.c
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-22 07:05:24-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

diff --git a/librz/arch/isa/hexagon/il_ops/hexagon_il_L2_ops.c b/librz/arch/isa/hexagon/il_ops/hexagon_il_L2_ops.c
@@ -1,9 +1,9 @@
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
-// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2024-03-16 06:22:39-05:00
+// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
+// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
+// Date of code generation: 2025-02-22 07:05:24-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator: