Clarify PTE update text

svadu.adoc

@@ -16,8 +16,8 @@ A/D bits. The A and D bits are managed by these extensions as follows:
   PTE updates caused by an explicit or an implicit memory accesses.            +
                                                                                +
   The PTE update must be atomic with respect to other accesses to the PTE, and
-  must atomically check that the PTE is valid and grants sufficient permissions
-  as part of conditionally making the update. Updates of the A bit may be
+  must atomically perform all tablewalk checks for that leaf PTE as part of, and
+  before, conditionally updating the PTE value. Updates of the A bit may be
   performed as a result of speculation, even if the associated memory access
   ultimately is not performed architecturally. However, updates to the D bit,
   resulting from an explicit store, must be exact (i.e., non-speculative), and