clarify explicit store behavior for D bit

svadu.adoc

@@ -20,10 +20,10 @@ A/D bits. The A and D bits are managed by these extensions as follows:
   as part of conditionally making the update. Updates of the A bit may be
   performed as a result of speculation, even if the associated memory access
   ultimately is not performed architecturally. However, updates to the D bit
-  must be exact (i.e., non-speculative), and observed in program order by the 
-  local hart. When two-stage address translation is active, updates of the D bit 
-  in G-stage PTEs may be performed as a result of speculative updates of the A 
-  bit in VS-stage PTEs.                                                        +
+  by an explicit store must be exact (i.e., non-speculative), and observed in
+  program order by the local hart. When two-stage address translation is active,
+  updates of the D bit in G-stage PTEs may be performed as a result of
+  speculative updates of the A bit in VS-stage PTEs.                           +
                                                                                +
   The PTE update must appear in the global memory order before the memory access
   that caused the PTE update and before any subsequent explicit memory access to