Merge pull request #19 from rsahita/topic/issue3

Addressing issue #3

chapter2.adoc

@@ -12,8 +12,10 @@ that can be held in an M-mode CSR and modifiable by the RDSM via CSR r/w
 instructions  - herewith called the `supervisor domain identifier` assigned to
 the hart. Supervisor domains are orthogonal to hart privilege levels and since
 Smmtt enables physical memory isolation, there is one CSR (per hart) managed by
-M-mode. Device side accesses are addressed in the `IO-MTT` extension. Isolation
-of data within a device is out of scope of this specification.
+M-mode. `Smsdid` is expected to be used in conjunction with `Smmtt` for physical
+memory isolation along with mechanisms such as `PMP` and `Smepmp`. Device side
+accesses are addressed in the `IO-MTT` extension. Isolation of data within a
+device is out of scope of this specification.
 
 * `Smmtt` (<<Smmtt>>) - An interface to set the access permissions for a memory
 region or page associated with a supervisor domain. This interface allows
@@ -29,7 +31,10 @@ the RDSM (except for when explicitly allowed by the RDSM). Privilege levels may
 affect changes in the MTT under purview of the Supervisor Domain Security
 Manager (SDSM) either through an SBI interface into M-mode (or may have the
 ability to edit MTT structures by virtue of how the MTT structure in memory is
-accessible to lower privilege levels).
+accessible to lower privilege levels). MTT and e(PMP) are always active.
+MTT may be configured to be `Bare` if granular memory access control
+is not required. The SDID
+CSR defined by `Smsdid` is used as defined.
 
 * `Svpams` (<<Svpams>>) - Physical address metadata selector - When access to
 memory that is shared by one or more supervisor domains is allowed by the MTT,

chapter3.adoc

@@ -69,6 +69,8 @@ addresses with access allowed/disallowed per page
 
 |2 |`Smmtt34rw` |Page-based supervisor domain protection for 34 bit
 physical addresses with RW permissions per page
+
+|3 |- |`_Reserved_`
 |===
 
 .Encoding of `mttp` `MODE` field for `XLEN=64`.