Changing .adoc to .edn for wavedrom files

src/a-st-ext.adoc

@@ -355,7 +355,7 @@ substantially easier to provide in some microarchitectural styles.
 [[sec:amo]]
 === "Zaamo" Extension for Atomic Memory Operations
 
-include::images/wavedrom/atomic-mem.adoc[]
+include::images/wavedrom/atomic-mem.edn[]
 
 The atomic memory operation (AMO) instructions perform read-modify-write
 operations for multiprocessor synchronization and are encoded with an

src/c-st-ext.adoc

@@ -217,7 +217,7 @@ For many RVC instructions, zero-valued immediates are disallowed and
 encoding space for other instructions requiring fewer operand bits.
 
 //[[cr-register]]
-//include::images/wavedrom/cr-register.adoc[]
+//include::images/wavedrom/cr-register.edn[]
 //.Compressed 16-bit RVC instructions
 //(((compressed, 16-bit)))
 
@@ -297,7 +297,7 @@ registers.
 
 ==== Stack-Pointer-Based Loads and Stores
 
-include::images/wavedrom/c-sp-load-store.adoc[]
+include::images/wavedrom/c-sp-load-store.edn[]
 [[c-sp-load-store]]
 //.Stack-Pointer-Based Loads and Stores--these instructions use the CI format.
 
@@ -334,7 +334,7 @@ register _rd_. It computes its effective address by adding the
 _zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It
 expands to `fld rd, offset(x2)`.
 
-include::images/wavedrom/c-sp-load-store-css.adoc[]
+include::images/wavedrom/c-sp-load-store-css.edn[]
 [[c-sp-load-store-css]]
 //.Stack-Pointer-Based Loads and Stores--these instructions use the CSS format.
 
@@ -446,7 +446,7 @@ _zero_-extended offset, scaled by 8, to the base address in register
 `fld rd′, offset(rs1′)`.
 
 [[c-cs-format-ls]]
-include::images/wavedrom/c-cs-format-ls.adoc[]
+include::images/wavedrom/c-cs-format-ls.edn[]
 //.Compressed, CS format load and store--these instructions use the CS format.
 (((compressed, cs-format load and store)))
 
@@ -490,7 +490,7 @@ instructions. As with base RVI instructions, the offsets of all RVC
 control transfer instructions are in multiples of 2 bytes.
 
 [[c-cj-format-ls]]
-include::images/wavedrom/c-cj-format-ls.adoc[]
+include::images/wavedrom/c-cj-format-ls.edn[]
 //.Compressed, CJ format load and store--these instructions use the CJ format.
 (((compressed, cj-format load and store)))
 
@@ -507,7 +507,7 @@ the jump (`pc+2`) to the link register, `x1`. C.JAL expands to
 `jal x1, offset`.
 
 [[c-cr-format-ls]]
-include::images/wavedrom/c-cr-format-ls.adoc[]
+include::images/wavedrom/c-cr-format-ls.edn[]
 //.Compressed, CR format load and store--these instructions use the CR format.
 (((compressed, cr-format load and store)))
 
@@ -535,7 +535,7 @@ bytes is only a very minor change to the base microarchitecture.
 ====
 
 [[c-cb-format-ls]]
-include::images/wavedrom/c-cb-format-ls.adoc[]
+include::images/wavedrom/c-cb-format-ls.edn[]
 //.Compressed, CB format load and store--these instructions use the CB format.
 (((compressed, cb-format load and store)))
 
@@ -562,7 +562,7 @@ The two constant-generation instructions both use the CI instruction
 format and can target any integer register.
 
 [[c-integer-const-gen]]
-include::images/wavedrom/c-integer-const-gen.adoc[]
+include::images/wavedrom/c-integer-const-gen.edn[]
 //.Integer constant generation format.
 (((compressed, integer constant generation)))
 
@@ -587,7 +587,7 @@ These integer register-immediate operations are encoded in the CI format
 and perform operations on an integer register and a 6-bit immediate.
 
 [[c-integer-register-immediate]]
-include::images/wavedrom/c-int-reg-immed.adoc[]
+include::images/wavedrom/c-int-reg-immed.edn[]
 //.Integer register-immediate format.
 (((compressed, integer register-immediate)))
 
@@ -620,7 +620,7 @@ always 16-byte aligned.
 ====
 
 [[c-ciw]]
-include::images/wavedrom/c-ciw.adoc[]
+include::images/wavedrom/c-ciw.edn[]
 //.CIW format.
 (((compressed, CIW)))
 C.ADDI4SPN is a CIW-format instruction that adds a _zero_-extended
@@ -632,7 +632,7 @@ _nzuimm_≠0; the code points with _nzuimm_=0 are
 reserved.
 
 [[c-ci]]
-include::images/wavedrom/c-ci.adoc[]
+include::images/wavedrom/c-ci.edn[]
 //.CI format.
 (((compressed, CI)))
 
@@ -650,7 +650,7 @@ all base ISAs, the code points with `_rd_=x0` are HINTs, except those
 with _shamt[5]_=1 in RV32C.
 
 [[c-srli-srai]]
-include::images/wavedrom/c-srli-srai.adoc[]
+include::images/wavedrom/c-srli-srai.edn[]
 //.C-SRLI-SRAI format.
 (((compressed, C.SRLI, C.SRAI)))
 
@@ -686,7 +686,7 @@ that RV128C will not be frozen at the same point as RV32C and RV64C, to
 allow evaluation of typical usage of 128-bit address-space codes.
 ====
 [[c-andi]]
-include::images/wavedrom/c-andi.adoc[]
+include::images/wavedrom/c-andi.edn[]
 //.C.ANDI format
 (((compressed, C.ANDI)))
 
@@ -698,7 +698,7 @@ expands to `andi rd′, rd′, imm`.
 ==== Integer Register-Register Operations
 
 [[c-cr]]
-include::images/wavedrom/c-int-reg-to-reg-cr-format.adoc[]
+include::images/wavedrom/c-int-reg-to-reg-cr-format.edn[]
 //C.CR format
 ((((compressed. C.CR))))
 These instructions use the CR format.
@@ -722,7 +722,7 @@ valid when `rs2≠x0` the code points with `rs2=x0` correspond to the C.JALR
 and C.EBREAK instructions. The code points with `rs2≠x0` and rd=x0 are HINTs.
 
 [[c-ca]]
-include::images/wavedrom/c-int-reg-to-reg-ca-format.adoc[]
+include::images/wavedrom/c-int-reg-to-reg-ca-format.edn[]
 //C.CA format
 ((((compressed. C.CA))))
 
@@ -771,7 +771,7 @@ improvement in static and dynamic compression.
 ==== Defined Illegal Instruction
 
 [[c-def-illegal-inst]]
-include::images/wavedrom/c-def-illegal-inst.adoc[]
+include::images/wavedrom/c-def-illegal-inst.edn[]
 ((((compressed. C.DIINST))))
 
 A 16-bit instruction with all bits zero is permanently reserved as an
@@ -791,7 +791,7 @@ non-existent memory regions.
 ==== NOP Instruction
 
 [[c-nop-instr]]
-include::images/wavedrom/c-nop-instr.adoc[]
+include::images/wavedrom/c-nop-instr.edn[]
 ((((compressed. C.NOPINSTR))))
 
 `C.NOP` is a CI-format instruction that does not change any user-visible
@@ -802,7 +802,7 @@ _imm_=0; the code points with _imm_≠0 encode HINTs.
 ==== Breakpoint Instruction
 
 [[c-breakpoint-instr]]
-include::images/wavedrom/c-breakpoint-instr.adoc[]
+include::images/wavedrom/c-breakpoint-instr.edn[]
 ((((compressed. C.BREAKPOINTINSTR))))
 
 Debuggers can use the `C.EBREAK` instruction, which expands to `ebreak`,

src/counters.adoc

@@ -27,7 +27,7 @@ Some execution environments might prohibit access to counters, for
 example, to impede timing side-channel attacks.
 ====
 
-include::images/wavedrom/counters-diag.adoc[]
+include::images/wavedrom/counters-diag.edn[]
 
 
 For base ISAs with XLEN≥64, CSR instructions can access

src/rv32.adoc

@@ -444,7 +444,7 @@ than the regular link register.
 Plain unconditional jumps (assembler pseudoinstruction J) are encoded as
 a JAL with _rd_=`x0`.
 
-include::images/wavedrom/ct-unconditional.adoc[]
+include::images/wavedrom/ct-unconditional.edn[]
 [[ct-unconditional]]
 //.The unconditional-jump instruction, JAL
 
@@ -462,7 +462,7 @@ Procedure returns in the standard calling convention (assembler
 pseudoinstruction RET) are encoded as a JALR with _rd_=`x0`, _rs1_=`x1`, and
 _imm_=0.
 
-include::images/wavedrom/ct-unconditional-2.adoc[]
+include::images/wavedrom/ct-unconditional-2.edn[]
 [[ct-unconditional-2]]
 //.The indirect unconditional-jump instruction, JALR
 
@@ -556,7 +556,7 @@ is sign-extended and added to the address of the branch instruction to
 give the target address. The conditional branch range is
 ±4 KiB.
 
-include::images/wavedrom/ct-conditional.adoc[]
+include::images/wavedrom/ct-conditional.edn[]
 [[ct-conditional]]
 //.Conditional branches
 

src/zicsr.adoc

@@ -24,7 +24,7 @@ CSR specifier is encoded in the 12-bit _csr_ field of the instruction
 held in bits 31-20. The immediate forms use a 5-bit zero-extended
 immediate encoded in the _rs1_ field.
 
-include::images/wavedrom/csr-instr.adoc[]
+include::images/wavedrom/csr-instr.edn[]
 
 The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in
 the CSRs and integer registers. CSRRW reads the old value of the CSR,

src/zimop.adoc

@@ -76,7 +76,7 @@ Their encoding allows future extensions to define them to read register
 
 The Zcmop extension depends upon the Zca extension.
 
-include::images/wavedrom/c-mop.adoc[]
+include::images/wavedrom/c-mop.edn[]
 [[c-mop]]
 
 NOTE: Very few suitable 16-bit encoding spaces exist.  This space was chosen