Add B standard extension

riscv · Mar 25, 2024 · cdb2585 · cdb2585
1 parent d69d777
commit cdb2585
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diff --git a/src/b-st-ext.adoc b/src/b-st-ext.adoc
@@ -1,6 +1,9 @@
 [[bits]]
 == "B" Standard Extension for Bit Manipulation, Version 1.0.0
 
+The B standard extension comprises instructions provided by the Zba, Zbb, and
+Zbs extensions.
+
 [[preface]]
 === Bit-manipulation a, b, c and s extensions grouped for public review and ratification
 
@@ -3898,4 +3901,4 @@ strcmp:
   ret
 
 .size   strcmp, .-strcmp
---
+--
diff --git a/src/machine.adoc b/src/machine.adoc
@@ -156,7 +156,7 @@ X +
 Y +
 Z
 |Atomic extension +
-_Reserved_ +
+B extension +
 Compressed extension +
 Double-precision floating-point extension +
 RV32E/64E base ISA +
@@ -192,6 +192,10 @@ supervisor modes respectively.
 
 The "X" bit will be set if there are any non-standard extensions.
 
+When "B" bit is 1, the implementation supports the instructions provided by the
+Zba, Zbb, and Zbs extensions. When "B" bit is 0, it indicates that the
+implementation may not support one or more of the Zba, Zbb, or Zbs extensions.
+
 [NOTE]
 ====
 The `misa` CSR exposes a rudimentary catalog of CPU features to

diff --git a/src/naming.adoc b/src/naming.adoc
@@ -182,6 +182,8 @@ e.g., RV32IMACV is legal, whereas RV32IMAVC is not.
 
 |16-bit Compressed Instructions |C |
 
+|B Extension |B |
+
 |Packed-SIMD Extensions |P |
 
 |Vector Extension |V |D