FESVR: Can't read a DM register when DMACTIVE=0 #392
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This was referenced Feb 10, 2020
aswaterman
approved these changes
Feb 10, 2020
timsifive
approved these changes
Feb 10, 2020
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As noted in discussion in chipsalliance/rocket-chip#2205, its not really allowed by the debug spec to read Debug Module DMI registers when DMACTIVE is 0. OpenOCD was fixed a while ago (riscv-collab/riscv-openocd@906635c) to not do this. FESVR has never been fixed.
This PR does not set DMACTIVE to 0 even when resuming a hart. This shouldn't have any actual impact on the performance since having DMACTIVE=1 doesn't necessarily do anything to the hart's execution (though it may prevent clock gating or other low-power mechanisms).