Adding support for the Zalasr (Load-acquire and store-release) extension

CHANGELOG.md

@@ -7,6 +7,9 @@ Please note the header `WIP-DEV` is to always remain indicating the changes done
 Only when a release to the main branch is done, the contents of the WIP-DEV are put under a
 versioned header while the `WIP-DEV` is left empty
 
+## [WIP-DEV] - 2024-05-08
+- Added support for Zalasr unratified extension
+
 ## [0.12.2] - 2024-03-06
 - Add Zfa support. (PR#60)
 - Initial covergroups for Zvk* instructions (PR#61)

riscv_ctg/data/template.yaml

@@ -12661,3 +12661,150 @@ ssrdp_u:
     #define ZICFISS_SETUP_DONE 1
     #endif
     TEST_SSRDP_OP(ssrdp, $rd, $swreg, $testreg, Umode)
+lb.aq:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'laqformat'
+  ea_align_data: '[0,1,2,3]'
+  template: |-
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,0,$offset,$inst,$ea_align)
+
+lh.aq:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'laqformat'
+  ea_align_data: '[0,1,2,3]'
+  template: |-
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,0,$offset,$inst,$ea_align)
+
+lw.aq:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'laqformat'
+  ea_align_data: '[0,1,2,3]'
+  template: |-
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,0,$offset,$inst,$ea_align)
+
+ld.aq:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  xlen: [64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'laqformat'
+  ea_align_data: '[0,1,2,3,4,5,6,7]'
+  template: |-
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,0,$offset,$inst,$ea_align)
+
+sb.rl:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'srlformat'
+  ea_align_data: '[0,1,2,3]'
+  template: |-
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,0,$offset,$inst,$ea_align)
+
+sh.rl:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'srlformat'
+  ea_align_data: '[0,1,2,3]'
+  template: |-
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,0,$offset,$inst,$ea_align)
+
+sw.rl:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'srlformat'
+  ea_align_data: '[0,1,2,3]'
+  template: |-
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,0,$offset,$inst,$ea_align)
+
+sd.rl:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  xlen: [64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'srlformat'
+  ea_align_data: '[0,1,2,3,4,5,6,7]'
+  template: |-
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,0,$offset,$inst,$ea_align)

riscv_ctg/generator.py

@@ -100,7 +100,9 @@ def get_rm(opcode):
     'ppbrrformat': ['rs1', 'rs2', 'rd'],
     'prrformat': ['rs1', 'rs2', 'rd'],
     'prrrformat': ['rs1', 'rs2', 'rs3', 'rd'],
-    'dcasrformat': ['rs1', 'rs2', 'rd']
+    'dcasrformat': ['rs1', 'rs2', 'rd'],
+    'laqformat': ['rs1', 'rd'],
+    'srlformat': ['rs1', 'rs2'],
 }
 ''' Dictionary mapping instruction formats to operands used by those formats '''
 
@@ -148,7 +150,9 @@ def get_rm(opcode):
     'ppbrrformat': '["rs1_val"] + simd_val_vars("rs2", xlen, 8)',
     'prrformat': '["rs1_val", "rs2_val"]',
     'prrrformat': "['rs1_val', 'rs2_val' , 'rs3_val']",
-    'dcasrformat': '["rs1_val", "rs2_val"]'
+    'dcasrformat': '["rs1_val", "rs2_val"]',
+    'laqformat': '["rs1_val"]',
+    'srlformat': '["rs1_val", "rs2_val"]'
 }
 ''' Dictionary mapping instruction formats to operand value variables used by those formats '''
 
@@ -256,7 +260,10 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str):
         self.is_fext = is_fext
         self.is_nan_box = is_nan_box
 
-        if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd"]:
+        if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',
+                      "jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr",
+                      "flw","fsw","fld","fsd",
+                      "lb.aq", "lh.aq", "lw.aq", "ld.aq", "sb.rl", "sh.rl", "sw.rl", "sd.rl"]:
             self.val_vars = self.val_vars + ['ea_align']
         self.template = opnode['template']
         self.opnode = opnode

sample_cgfs/rv32zalasr.cgf

@@ -0,0 +1,87 @@
+# cover group format file for Zalasr extension
+lb.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'lb.aq' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+      'ea_align == 1' : 0
+      'ea_align == 2' : 0
+      'ea_align == 3' : 0
+lh.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'lh.aq' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+      'ea_align == 2' : 0
+lw.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'lw.aq' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+sb.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'sb.rl' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+      <<: *sfmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+      'ea_align == 1' : 0
+      'ea_align == 2' : 0
+      'ea_align == 3' : 0
+sh.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'sh.rl' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+      <<: *sfmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+      'ea_align == 2' : 0
+sw.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'sw.rl' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+      <<: *sfmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0

sample_cgfs/rv64zalasr.cgf

@@ -0,0 +1,113 @@
+# cover group format file for Zalasr extension
+lb.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'lb.aq' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+      'ea_align == 1' : 0
+      'ea_align == 2' : 0
+      'ea_align == 3' : 0
+lh.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'lh.aq' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+      'ea_align == 2' : 0
+lw.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'lw.aq' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+ld.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'ld.aq' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+sb.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'sb.rl' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+      <<: *sfmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+      'ea_align == 1' : 0
+      'ea_align == 2' : 0
+      'ea_align == 3' : 0
+sh.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'sh.rl' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+      <<: *sfmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+      'ea_align == 2' : 0
+sw.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'sw.rl' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+      <<: *sfmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0
+sd.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    mnemonics: 
+      'sd.rl' : 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+      <<: *sfmt_op_comb
+    val_comb:
+      'ea_align == 0' : 0