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Merge pull request #76 from riscv-software-src/warl-fix-and-svnapot-s…
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…upport

clean up warl and svnapot support added
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@neelgala
neelgala committed Mar 9, 2022
2 parents 8c01729 + 2347731 commit e8e1703
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Showing 6 changed files with 38 additions and 39 deletions.
1 change: 1 addition & 0 deletions .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -10,3 +10,4 @@ __pycache__/*
*.pyc

riscv_config_work/*
.python-version
5 changes: 5 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -2,6 +2,11 @@

This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).

## [2.13.0] - 2022-03-09
- add support for detection of svnapot in ISA string
- genralize conversion of hex, oct, bin values to int in warl functions
- machine flat schema to include wlrl types as well

## [2.12.1] - 2021-12-18
### Fixed

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2 changes: 1 addition & 1 deletion riscv_config/__init__.py
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
from pkgutil import extend_path
__path__ = extend_path(__path__, __name__)
__version__ = '2.12.1'
__version__ = '2.13.0'
10 changes: 6 additions & 4 deletions riscv_config/schemaValidator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -72,17 +72,19 @@ def _check_with_capture_isa_specifics(self, field, value):
else:
self._error(field, "Invalid width in ISA.")
#ISA checks
str_match = re.findall(r'([^\d]*?)(?!_)*(Z.*?)*(_|$)',value,re.M)
str_match = re.findall('(?P<stdisa>[^\d]*?)(?!_)*(?P<zext>Z.*?)*(?P<sext>S[a-z]*)*(_|$)',value)
extension_list= []
standard_isa = ''
for match in str_match:
stdisa, z, ignore = match
stdisa, zext, sext, ignore = match
if stdisa != '':
for e in stdisa:
extension_list.append(e)
standard_isa = stdisa
if z != '':
extension_list.append(z)
if zext != '':
extension_list.append(zext)
if sext != '':
extension_list.append(sext)
# check ordering of ISA
canonical_ordering = 'IEMAFDQLCBJKTPVNSHU'
order_index = {c: i for i, c in enumerate(canonical_ordering)}
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4 changes: 3 additions & 1 deletion riscv_config/schemas/schema_isa.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,7 @@ hart_schema:
# - The ISA string must be specified as per the convention mentioned in the specifications(like subsequent Z extensions must be separated with an '_')

ISA: { type: string, required: true, check_with: capture_isa_specifics,
regex: "^RV(32|64|128)[IE]+[ABCDEFGHJKLMNPQSTUVX]*(Zicsr|Zifencei|Zihintpause|Zam|Ztso|Zkne|Zknd|Zknh|Zkse|Zksh|Zkg|Zkb|Zkr|Zks|Zkn|Zba|Zbc|Zbb|Zbp|Zbr|Zbm|Zbs|Zbe|Zbf|Zbt|Zmmul){,1}(_Zicsr){,1}(_Zifencei){,1}(_Zihintpause){,1}(_Zmmul){,1}(_Zam){,1}(_Zba){,1}(_Zbb){,1}(_Zbc){,1}(_Zbe){,1}(_Zbf){,1}(_Zbm){,1}(_Zbp){,1}(_Zbr){,1}(_Zbs){,1}(_Zbt){,1}(_Zkb){,1}(_Zkg){,1}(_Zkr){,1}(_Zks){,1}(_Zkn){,1}(_Zknd){,1}(_Zkne){,1}(_Zknh){,1}(_Zkse){,1}(_Zksh){,1}(_Ztso){,1}$" }
regex: "^RV(32|64|128)[IE]+[ABCDEFGHJKLMNPQSTUVX]*(Zicsr|Zifencei|Zihintpause|Zam|Ztso|Zkne|Zknd|Zknh|Zkse|Zksh|Zkg|Zkb|Zkr|Zks|Zkn|Zba|Zbc|Zbb|Zbp|Zbr|Zbm|Zbs|Zbe|Zbf|Zbt|Zmmul|Svnapot){,1}(_Zicsr){,1}(_Zifencei){,1}(_Zihintpause){,1}(_Zmmul){,1}(_Zam){,1}(_Zba){,1}(_Zbb){,1}(_Zbc){,1}(_Zbe){,1}(_Zbf){,1}(_Zbm){,1}(_Zbp){,1}(_Zbr){,1}(_Zbs){,1}(_Zbt){,1}(_Zkb){,1}(_Zkg){,1}(_Zkr){,1}(_Zks){,1}(_Zkn){,1}(_Zknd){,1}(_Zkne){,1}(_Zknh){,1}(_Zkse){,1}(_Zksh){,1}(_Ztso){,1}(_Svnapot){,1}$" }

###
#User_Spec_Version
Expand Down Expand Up @@ -295,6 +295,7 @@ hart_schema:
oneof:
- schema: {ro_constant: {type: integer, max: 0xFFFFFFFF}}
- schema: { warl: *ref_warl }
- schema: { wlrl: *ref_wlrl }
default:
ro_constant: 0
accessible:
Expand All @@ -316,6 +317,7 @@ hart_schema:
oneof:
- schema: {ro_constant: {type: integer, max: 0xFFFFFFFFFFFFFFFF}}
- schema: { warl: *ref_warl }
- schema: { wlrl: *ref_wlrl }
default:
ro_constant: 0
accessible:
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55 changes: 22 additions & 33 deletions riscv_config/warl.py
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ def prevsum(self, i, k):

def islegal(self, value, dependency_vals=[]):
is_legal = False
logger.debug('Checking for isLegal for WARL: \n\t' +
logger.debug('Checking for isLegal for WARL: \n' +
utils.pretty_print_yaml(self.warl) + '\n With following args:'\
+ 'val : ' + str(value) + ' dep_vals :'+
str(dependency_vals))
Expand All @@ -46,21 +46,15 @@ def islegal(self, value, dependency_vals=[]):
if not bitmask: # if its not a bitmask
if ":" in csr_vals: # range is specified
[base, bound] = csr_vals.split(':')
if 'x' in base:
base = int(base,16)
else:
base = int(base,10)
if 'x' in bound:
bound = int(bound,16)
else:
bound = int(bound,10)
base = int(base, 0)
bound = int(bound, 0)
if value >= base and value <= bound: # check legal range
part_legal = True
else:
l_vals = csr_vals.split(',')
legal_vals = []
for i in l_vals :
legal_vals.append(int(i,16))
legal_vals.append(int(i,0))
if value in legal_vals:
part_legal = True
else: # in case of bitmask there are no illegal values
Expand Down Expand Up @@ -100,17 +94,15 @@ def islegal(self, value, dependency_vals=[]):
# check if the dependency value is satisfied.
if ":" in dep_vals: # range is specified
[base, bound] = dep_vals.split(':')
if 'x' in base:
base = int(base,16)
if 'x' in bound:
bound = int(bound,16)
base = int(base, 0)
bound = int(bound, 0)
if recvd_val >= base and recvd_val <= bound: # check legal range
dep_satified = True
else:
l_vals = dep_vals.split(',')
legal_vals = []
for i in l_vals :
legal_vals.append(int(i,16))
legal_vals.append(int(i,0))
if recvd_val in legal_vals:
dep_satified = True

Expand All @@ -125,17 +117,15 @@ def islegal(self, value, dependency_vals=[]):
if not bitmask: # if its not a bitmask
if ":" in csr_vals: # range is specified
[base, bound] = csr_vals.split(':')
if 'x' in base:
base = int(base,16)
if 'x' in bound:
bound = int(bound,16)
base = int(base, 0)
bound = int(bound, 0)
if trunc_val >= base and trunc_val <= bound: # check legal range
part_legal = True
else:
l_vals = csr_vals.split(',')
legal_vals = []
for i in l_vals :
legal_vals.append(int(i,16))
legal_vals.append(int(i,0))
if trunc_val in legal_vals:
part_legal = True
else: # in case of bitmask there are no illegal values
Expand Down Expand Up @@ -196,9 +186,8 @@ def update(self, curr_val, wr_val, dependency_vals=[]):
for i1 in range(len(dependency_vals)):
if dependency_vals[i1] == int(mode[i1]):
if op != []:
if int(wr_val,
16) in range(int(z[0], 16),
int(z[1], 16)):
if int(wr_val, 0) in range(int(z[0], 0),
int(z[1], 0)):
j = i
flag1 = 1
break
Expand All @@ -220,7 +209,7 @@ def update(self, curr_val, wr_val, dependency_vals=[]):
self.warl['wr_illegal'][i])
if op != []:
z = re.split("\:", op[0])
if int(wr_val, 16) in range(int(z[0], 16), int(z[1], 16)):
if int(wr_val, 0) in range(int(z[0], 0), int(z[1], 0)):
j = i
flag1 = 1
break
Expand Down Expand Up @@ -260,7 +249,7 @@ def update(self, curr_val, wr_val, dependency_vals=[]):
l = self.legal(dependency_vals)
for i in range(len(l)):
if len(l[i]) == 1:
a.append(abs(int(wr_val, 16) - int(l[i][0], 16)))
a.append(abs(int(wr_val, 0) - int(l[i][0], 0)))
for i in range(len(a) - 1, -1, -1):
if a[i] == min(a):
j = i
Expand All @@ -274,7 +263,7 @@ def update(self, curr_val, wr_val, dependency_vals=[]):
l = self.legal(dependency_vals)
for i in range(len(l)):
if len(l[i]) == 1:
a.append(abs(int(wr_val, 16) - int(l[i][0], 16)))
a.append(abs(int(wr_val, 0) - int(l[i][0], 0)))
for i in range(len(a)):
if a[i] == min(a):
j = i
Expand All @@ -286,7 +275,7 @@ def update(self, curr_val, wr_val, dependency_vals=[]):
elif wr.lower().strip() == "nextup":
l = self.legal(dependency_vals)
for i in range(len(l)):
if int(l[i][0], 16) > int(wr_val, 16) and len(l[i]) == 1:
if int(l[i][0], 0) > int(wr_val, 0) and len(l[i]) == 1:
j = i
flag2 = 1
break
Expand All @@ -298,7 +287,7 @@ def update(self, curr_val, wr_val, dependency_vals=[]):
elif wr.lower().strip() == "nextdown":
l = self.legal(dependency_vals)
for i in range(len(l)):
if int(l[i][0], 16) > int(wr_val, 16) and len(l[i]) == 1:
if int(l[i][0], 0) > int(wr_val, 0) and len(l[i]) == 1:
j = i
flag2 = 1
break
Expand Down Expand Up @@ -338,7 +327,7 @@ def update(self, curr_val, wr_val, dependency_vals=[]):
return y[0]

elif wr.lower().strip() == "addr":
wr = format(int(wr_val, 16),
wr = format(int(wr_val, 0),
'#0{}b'.format(4 * self.bitsum + 2))
wr = wr[2:]
if wr[0:1] == '0':
Expand All @@ -347,7 +336,7 @@ def update(self, curr_val, wr_val, dependency_vals=[]):
wr_final = '0' + wr[1:]
else:
print("Invalid binary bit")
return hex(int(wr_final, 2))
return hex(int(wr_final, 0))

else:
return "Invalid update mode"
Expand All @@ -358,9 +347,9 @@ def update(self, curr_val, wr_val, dependency_vals=[]):
z = re.findall(
r'\s*.*\s*\[(.*)\]\s*{}\s*\[.*?,.*?\]'.format("bitmask"), inp1)
y = re.split("\,", x[0])
bitmask = int(y[0], 16)
fixedval = int(y[1], 16)
currval = int(wr_val, 16)
bitmask = int(y[0], 0)
fixedval = int(y[1], 0)
currval = int(wr_val, 0)
legal = ((currval & bitmask) | fixedval)
return hex(legal)

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