Csr tests and accessiblity changes (#29)

* Changing implemented to accessible. "Closes #14" * Fixed definitions for wlrl nodes and fields dependent on NSU extensions. * Doc update.
riscv-software-src · Apr 7, 2020 · 4597f25 · 4597f25
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diff --git a/.travis.yml b/.travis.yml
@@ -20,7 +20,7 @@ deploy:
  api_key: $github_access_token
  file_glob: true
  file: docs/build/latex/*.pdf
- cleanup: true
+ cleanup: false
  on:
    repo: riscv/riscv-config
    branch: master

diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -2,6 +2,11 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## 2.2.0 - 2020-04-07
+### Changed
+- Renamed the 'implemented' field  in rv32 and rv64 nodes to 'accessible'.
+- Modified appropriate definitions for fields dependent on specific extensions like NSU.
+
 ## 2.1.1 - 2020-03-29
 ## Fixed
 - doc issue for mtimecmp

diff --git a/docs/source/yaml-specs.rst b/docs/source/yaml-specs.rst
@@ -11,7 +11,7 @@ ISA YAML Spec
 
 **NOTE**:
 
-  1. All fields accept values as integers or hexadecimals(can be used interchangeably) unless specified otherwise.
+  1. All integer fields accept values as integers or hexadecimals(can be used interchangeably) unless specified otherwise.
   2. An elaborate example of the full-fledge ISA-YAML file can be found here: `ISA-YAML <https://github.com/riscv/riscv_config/blob/master/examples/template_isa.yaml>`_
 
 .. include:: schema_isa.rst
@@ -34,16 +34,16 @@ CSRs with sub-fields
                                             # of the all reset values of the sub-fields 
     rv32:                                   # this node and its subsequent fields can exist 
                                             # if [M/S/U]XL value can be 1
-      implemented: <boolean>                # indicates if the csr exists in rv32 mode or not. 
+      accessible: <boolean>                 # indicates if the csr is accessible in rv32 mode or not. 
                                             # When False, all fields below will be trimmed off 
                                             # in the checked yaml. False also indicates that 
-                                            # access-exception should be generated
+                                            # access-exception should be generated. 
       fields:                               # a quick summary of the list of all fields of the 
                                             # csr including a list of WPRI fields of the csr.
         - <field_name1>
         - <field_name2>
-        - - [30,23]                         # A list which contains a squashed pair 
-          - 6                               # (of form [msb,lsb]) of all WPRI bits within the 
+        - - [23,30]                         # A list which contains a squashed pair 
+          - 6                               # (of form [lsb,msb]) of all WPRI bits within the 
                                             # csr. Does not exist if there are no WPRI bits
   
       <field_name1>:                        # name of the field
@@ -56,7 +56,7 @@ CSRs with sub-fields
                                             # or not. When False, all 
                                             # fields below this will be trimmed.
         type:                               # type of field. Can be only one of the following
-          wlrl: [list of ranges]            # field is wlrl and the list of legal values.
+          wlrl: [list of value-descriptors] # field is wlrl and the set of legal values.
           ro_constant: <hex>                # field is readonly and will return the same value.
           ro_variable: True                 # field is readonly but the value returned depends 
                                             # on other arch-states
@@ -66,11 +66,11 @@ CSRs with sub-fields
             wr_illegal: [list of warl-string]           
     rv64:                                   # this node and its subsequent fields can exist 
                                             # if [M/S/U]XL value can be 2
-      implemented: <boolean>                # indicates if this register exists in rv64 mode 
+      accessible: <boolean>                 # indicates if this register exists in rv64 mode 
                                             # or not. Same definition as for rv32 node.
     rv128:                                  # this node and its subsequent fields can exist if 
                                             # [M/S/U]XL value can be 3
-      implemented: <boolean>                # indicates if this register exists in rv128 mode 
+      accessible: <boolean>                 # indicates if this register exists in rv128 mode 
                                             # or not. Same definition as for rv32 node.                          
 
 CSRs without sub-fields
@@ -86,17 +86,17 @@ CSRs without sub-fields
                                           # of the all reset values of the sub-fields 
     rv32:                                 # this node and its subsequent fields can exist 
                                           # if [M/S/U]XL value can be 1
-      implemented: <boolean>              # indicates if the csr exists in rv32 mode or not. 
+      accessible: <boolean>               # indicates if the csr is accessible in rv32 mode or not. 
                                           # When False, all fields below will be trimmed off 
                                           # in the checked yaml. False also indicates that 
                                           # access-exception should be generated
-      fields:                             # This should be empty always.
+      fields: []                          # This should be empty always.
       shadow: <csr-name>::<register>      # which this register shadows,'none' indicates that 
                                           # this register does not shadow anything.
       msb: <int>                          # msb index of the csr. max: 31, min:31
       lsb: <int>                          # lsb index of the csr. max: 0, min:0
       type:                               # type of field. Can be only one of the following
-        wlrl: [list of ranges]            # field is wlrl and the list of legal values.
+        wlrl: [list of value-descriptors] # field is wlrl and the set of legal values.
         ro_constant: <hex>                # field is readonly and will return the same value.
         ro_variable: True                 # field is readonly but the value returned depends 
                                           # on other arch-states
@@ -106,11 +106,11 @@ CSRs without sub-fields
           wr_illegal: [list of warl-string]           
     rv64:                                 # this node and its subsequent fields can exist 
                                           # if [M/S/U]XL value can be 2
-      implemented: <boolean>              # indicates if this register exists in rv64 mode 
+      accessible: <boolean>               # indicates if this register exists in rv64 mode 
                                           # or not. Same definition as for rv32 node.
     rv128:                                # this node and its subsequent fields can exist if 
                                           # [M/S/U]XL value can be 3
-      implemented: <boolean>              # indicates if this register exists in rv128 mode 
+      accessible: <boolean>              # indicates if this register exists in rv128 mode 
 
 Constraints
 -----------
@@ -120,7 +120,7 @@ Each CSR undergoes the following checks:
   1. All implemented fields at the csr-level, if set to True, are checked if
      they comply with the supported_xlen field of the ISA yaml.
   2. The reset-val is checked against compliance with the type field specified
-     by the user.
+     by the user. All unimplemented fields are considered to be hardwired to 0.
 
 For each of the above templates the following fields for all standard CSRs
 defined by the spec are frozen and **CANNOT** be modified by the user.
@@ -152,7 +152,7 @@ Following is an example of how a user can define the mtvec csr in the input ISA
   mtvec:
   reset-val: 0x80010000
   rv32:
-    implemented: true
+    accessible: true
     base:
       implemented: true
       type:                             
@@ -186,7 +186,7 @@ above user-input:
       priv_mode: M
       reset-val: 0x80010000
       rv32:
-        implemented: true
+        accessible: true
         base:
           implemented: true
           type:
@@ -221,7 +221,7 @@ above user-input:
         - mode
         - base 
       rv64:
-        implemented: false
+        accessible: false
 
 WARL field Definition
 =====================

diff --git a/examples/rv32i_isa.yaml b/examples/rv32i_isa.yaml
@@ -2,31 +2,29 @@ ISA: RV32IMAFCZicsr_Zifencei
 User_Spec_Version: '2.3'
 supported_xlen: [32]
 misa:
-  reset-val: 0x40001125
-  rv32:
-    implemented: true
-    mxl:
-      implemented: true
-      type:
-        ro_constant: [0x01]
-    extensions:
-      implemented: true
-      type:
-        ro_constant: [0x1125]
-  rv64:
-    implemented: false
+ reset-val: 0x40001125
+ rv32:
+   accessible: true
+   mxl:
+     implemented: true
+     type:
+       ro_constant: [0x01]
+   extensions:
+     implemented: true
+     type:
+       ro_constant: [0x1125]
 mvendorid:
   reset-val: 0xdeadbeef
   rv32:
-    implemented: true
+    accessible: true
     type:
       ro_constant: [0xdeadbeef]
   rv64:
-    implemented: false
+    accessible: false
 mtvec:
   reset-val: 0x80010000
   rv32:
-    implemented: true
+    accessible: true
     base:
       implemented: true
       type:                             

diff --git a/examples/rv64i_isa.yaml b/examples/rv64i_isa.yaml
@@ -3,9 +3,9 @@ supported_xlen: [64]
 misa:
   reset-val: 0x8000000000000100
   rv32:
-    implemented: false
+    accessible: false
   rv64:
-    implemented: true
+    accessible: true
     mxl:
       implemented: true
       type:
@@ -17,17 +17,15 @@ misa:
 mvendorid:
   reset-val: 0xdeadbeef
   rv32:
-    implemented: false
-    type:
-      ro_constant: [0xdeadbeef]
+    accessible: false
   rv64:
-    implemented: true
+    accessible: true
     type:
       ro_constant: [0xdeadbeef]
 mtvec:
   reset-val: 0x0000000080000000
   rv64:
-    implemented: true
+    accessible: true
     base:
       implemented: true
       type:                             
@@ -49,30 +47,4 @@ mtvec:
           legal: 
             - "mode[1:0] in [0x0:0x1] # Range of 0 to 1 (inclusive)"
           wr_illegal:
-            - "Unchanged"
-medeleg:
-  reset-val: 0x800  
-  rv32:
-     implemented: false
-  rv64:
-     implemented: false
-
-mideleg:
-  rv32:
-     implemented: false
-
-  rv64:
-     implemented: false
-
-sedeleg: 
-  reset-val: 0x800
-  rv32:
-     implemented: false
-  rv64:
-     implemented: false
-
-sideleg:
-  rv32:
-     implemented: false
-  rv64:
-     implemented: false
+            - "Unchanged"
diff --git a/riscv_config/__init__.py b/riscv_config/__init__.py
@@ -1,3 +1,3 @@
 from pkgutil import extend_path
 __path__ = extend_path(__path__, __name__)
-__version__ = "2.1.1"
+__version__ = "2.2.0"