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eclic: move eclic-mode-hack.S into Rust #55

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@rmsyn rmsyn commented May 23, 2023

Uses inline assembly to move the code from eclic-mode-hack.S into Rust.

The generated assembly is different. This commit should be reverted if regressions are noticed on real hardware.

@rmsyn rmsyn marked this pull request as draft May 23, 2023 03:31
".weak TIMER0_UP",
".weak TIMER0_TRG_CMT",
".weak TIMER0_CHANNEL",
".weak TIMER1",
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Raises a warning when compiling longan-nano/examples/interrupt

warning: TIMER1 changed binding to STB_WEAK
   |
note: instantiated into assembly here
  --> <inline asm>:33:1
   |
33 | .weak TIMER1

The timer interrupt fires, but only once at the beginning of execution.

Not sure how to solve this...

Using global_asm raises a TIMER1 changed binding to STB_GLOBAL error, and the build fails.

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@Disasm Disasm May 23, 2023

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This part and vectors should be global_asm because declaring it as a function may add a few instructions in the beginning and all the handler addresses will become shifted in this case. In any case, this is not code, so should not be callable.

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This part and vectors should be global_asm because declaring it as a function may add a few instructions in the beginning and all the handler addresses will become shifted in this case.

I completely agree, but when I tried to make it global_asm it raises an error in the longan-nano example code:

error: TIMER1 changed binding to STB_GLOBAL

That error occurs both with the interrupt macro from gd32vf103-pac, and the current code from the master branch.

Do you think it would help to implement a hand-written proc-macro, similar to what's in cortex-m and avr-device?

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Something is strange here. I got different results for debug and release builds:

% nm target/riscv32imac-unknown-none-elf/debug/examples/interrupt | grep " TIMER1"
08000568 T TIMER1
% nm target/riscv32imac-unknown-none-elf/release/examples/interrupt | grep " TIMER1"
080001c2 W TIMER1

It's ok when STB_GLOBAL is used (like in debug here), but STB_WEAK looks wrong. Maybe each interrupt handler needs a default implementation like was done in stm32f1, for example. It provides device.x with a lot of lines of the following format PROVIDE(TIM4 = DefaultHandler); and then an array is created with all the handlers: https://docs.rs/stm32f1/latest/src/stm32f1/stm32f103/mod.rs.html#82-177

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@rmsyn rmsyn May 27, 2023

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Moved everything into a global_asm block, and use a device.x file in the longan-nano example.

Using the device.x file to define the default handlers clears the STB_WEAK/GLOBAL errors, but the blinky still stays static (constantly on after 1 second). Not sure what is causing the error.

Edit: Maybe the lack of ilp32 calling convention/ABI? IDK, but I'm putting this work on hold for now. There doesn't seem to be much benefit (it's still assembly, just using the Rust/cargo build system). Ultimately, I think waiting for something like rust-lang/rust#111891 to land would probably be better.

rmsyn added 3 commits May 26, 2023 04:33
Updates cargo dependencies, and removes the deprecated `bare_metal::Nr`
trait.

The `bare_metal::Nr` is no longer present in the latest version, and all
usage in this HAL are easily replaced by directly converting the
`Interrupt` enum to a base integer type.
Adds `.option +zicsr` to `eclic-mode-hack.S` to fix a failure to
assemble with recent versions of `riscv64-unknown-elf-gcc` (e.g.
12.2.0).
Updates the precompiled `bin/gd32vf103xx-hal.a` part of the library.
@rmsyn rmsyn force-pushed the eclic-asm branch 2 times, most recently from d210ecf to 51a9fbd Compare May 27, 2023 20:03
Uses inline assembly to move the code from `eclic-mode-hack.S` into
Rust.

The generated assembly is different. This commit should be reverted if
regressions are noticed on real hardware.
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2 participants