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StarFive: Add JH7110 ACT Test Report
Signed-off-by: Yilun Xie <yilun.xie@starfivetech.com>
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StarFive/Dubhe-90-2023-12-14/Dubhe-90-2023-12-14-notes.txt
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CPU: Dubhe-90 | ||
bit_date: 20231027 | ||
bit_commit: fd548641dc49fd8d2a4d4a423eac76a41b0111ed | ||
bit_branch: lsu_re | ||
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Toolchain: 2023.12.14 | ||
Toolchain_commit: 99e2d2bac5144f5152ba6d3fbf04bdd9b9ba4381 | ||
Toolchain_path: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.12.14/riscv64-glibc-ubuntu-20.04-llvm-nightly-2023.12.14-nightly.tar.gz | ||
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ref_model: spike | ||
ref_mode_commit: a729aff03d0a1bd8fa179f636b4b5f21da28b75b | ||
ref_mode_commit_date: 2023 Dec 11 GMT+8 | ||
ref_model_path: https://github.com/riscv-software-src/riscv-isa-sim.git | ||
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ACT_framework: riscof 1.25.3 | ||
ACT_commit: a25e3155d3a62a042a2c5d976b386e3df5874d70 | ||
ACT_commit_date: 2023 Jan 30 GMT+8 | ||
ACT_path: https://github.com/riscv/riscof.git | ||
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riscv-arch-test: 3.8.0 | ||
riscv-arch-test_commit: f484d91992a438870f2412ea6d1219631f40b6c0 | ||
riscv-arch-test_commit_date: 2023 Oct 27 GMT+8 | ||
riscv-arch-test_path: https://github.com/riscv-non-isa/riscv-arch-test.git |
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hart_ids: [0] | ||
hart0: | ||
ISA: RV64IMAFDCSHUZicsr_Zicntr_Zifencei_Zihintpause_Zba_Zbb_Zbc_Zbs | ||
physical_addr_sz: 56 | ||
User_Spec_Version: '2.2' | ||
supported_xlen: [64] | ||
misa: | ||
reset-val: 0x80000000001411AD | ||
rv64: | ||
accessible: true | ||
mxl: | ||
implemented: true | ||
type: | ||
warl: | ||
dependency_fields: [] | ||
legal: | ||
- mxl[1:0] in [0x2] | ||
wr_illegal: | ||
- Unchanged | ||
extensions: | ||
implemented: true | ||
type: | ||
warl: | ||
dependency_fields: [] | ||
legal: | ||
- extensions[25:0] bitmask [0x01411AD, 0x0000000] | ||
wr_illegal: | ||
- Unchanged | ||
mvendorid: | ||
rv32: | ||
accessible: false | ||
rv64: | ||
accessible: true | ||
fields: [] | ||
shadow: | ||
shadow_type: rw | ||
msb: 31 | ||
lsb: 0 | ||
type: | ||
ro_constant: 0 | ||
address: 3857 | ||
priv_mode: M | ||
reset-val: 0 | ||
marchid: | ||
rv32: | ||
accessible: false | ||
rv64: | ||
accessible: true | ||
fields: [] | ||
shadow: | ||
shadow_type: rw | ||
msb: 63 | ||
lsb: 0 | ||
type: | ||
ro_constant: 0 | ||
address: 3858 | ||
priv_mode: M | ||
reset-val: 0 | ||
mimpid: | ||
rv32: | ||
accessible: false | ||
rv64: | ||
accessible: true | ||
fields: [] | ||
shadow: | ||
shadow_type: rw | ||
msb: 63 | ||
lsb: 0 | ||
type: | ||
ro_constant: 0 | ||
address: 3859 | ||
priv_mode: M | ||
reset-val: 0 |
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