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[Clang][XTHeadVector] Add vector unit-stride segment load/store intri…
…nsics (llvm#56) * [Clang][XTHeadVector] Add `th_vlseg<nf>e<eew>_v` * [Clang][XTHeadVector] Add `th_vlseg<nf>e<eew>ff_v` * [Clang][XTHeadVector] Add `th_vlseg<nf><b/h/w>_v` * [Clang][XTHeadVector] Fix Unit-stride segment load * [Clang][XTHeadVector] Test Unit-stride segment load * [Clang][XTHeadVector] Add Unit-stride segment store * [Clang][XTHeadVector] Test Unit-stride segment store * [NFC][XTHeadVector] Update README
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16 changes: 16 additions & 0 deletions
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clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2b.c
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| @@ -0,0 +1,16 @@ | ||
| // RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ | ||
| // RUN: -disable-O0-optnone -emit-llvm %s -o - | \ | ||
| // RUN: opt -S -passes=mem2reg | \ | ||
| // RUN: FileCheck --check-prefix=CHECK-RV64 %s | ||
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| #include <riscv_vector.h> | ||
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| // CHECK-RV64-LABEL: define dso_local { <vscale x 8 x i8>, <vscale x 8 x i8> } @test_th_vlseg2b_v_i8m1x2 | ||
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.th.vlseg2b.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> poison, ptr [[BASE]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]] | ||
| // | ||
| vint8m1x2_t test_th_vlseg2b_v_i8m1x2(const int8_t *base, size_t vl) { | ||
| return __riscv_th_vlseg2b_v_i8m1x2(base, vl); | ||
| } |
96 changes: 96 additions & 0 deletions
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clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e16.c
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| @@ -0,0 +1,96 @@ | ||
| // RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ | ||
| // RUN: -disable-O0-optnone -emit-llvm %s -o - | \ | ||
| // RUN: opt -S -passes=mem2reg | \ | ||
| // RUN: FileCheck --check-prefix=CHECK-RV64 %s | ||
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| #include <riscv_vector.h> | ||
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| // CHECK-RV64-LABEL: define dso_local { <vscale x 4 x half>, <vscale x 4 x half> } @test_th_vlseg2e16_v_f16m1x2 | ||
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x half>, <vscale x 4 x half> } @llvm.riscv.th.vlseg2e.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> poison, ptr [[BASE]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret { <vscale x 4 x half>, <vscale x 4 x half> } [[TMP0]] | ||
| // | ||
| vfloat16m1x2_t test_th_vlseg2e16_v_f16m1x2(const _Float16 *base, size_t vl) { | ||
| return __riscv_th_vlseg2e16_v_f16m1x2(base, vl); | ||
| } | ||
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| // CHECK-RV64-LABEL: define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_th_vlseg2e16_v_f16m2x2 | ||
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.riscv.th.vlseg2e.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> poison, ptr [[BASE]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret { <vscale x 8 x half>, <vscale x 8 x half> } [[TMP0]] | ||
| // | ||
| vfloat16m2x2_t test_th_vlseg2e16_v_f16m2x2(const _Float16 *base, size_t vl) { | ||
| return __riscv_th_vlseg2e16_v_f16m2x2(base, vl); | ||
| } | ||
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| // CHECK-RV64-LABEL: define dso_local { <vscale x 16 x half>, <vscale x 16 x half> } @test_th_vlseg2e16_v_f16m4x2 | ||
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x half>, <vscale x 16 x half> } @llvm.riscv.th.vlseg2e.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> poison, ptr [[BASE]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret { <vscale x 16 x half>, <vscale x 16 x half> } [[TMP0]] | ||
| // | ||
| vfloat16m4x2_t test_th_vlseg2e16_v_f16m4x2(const _Float16 *base, size_t vl) { | ||
| return __riscv_th_vlseg2e16_v_f16m4x2(base, vl); | ||
| } | ||
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| // CHECK-RV64-LABEL: define dso_local { <vscale x 4 x i16>, <vscale x 4 x i16> } @test_th_vlseg2e16_v_i16m1x2 | ||
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.th.vlseg2e.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> poison, ptr [[BASE]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]] | ||
| // | ||
| vint16m1x2_t test_th_vlseg2e16_v_i16m1x2(const int16_t *base, size_t vl) { | ||
| return __riscv_th_vlseg2e16_v_i16m1x2(base, vl); | ||
| } | ||
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| // CHECK-RV64-LABEL: define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_th_vlseg2e16_v_i16m2x2 | ||
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.th.vlseg2e.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> poison, ptr [[BASE]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]] | ||
| // | ||
| vint16m2x2_t test_th_vlseg2e16_v_i16m2x2(const int16_t *base, size_t vl) { | ||
| return __riscv_th_vlseg2e16_v_i16m2x2(base, vl); | ||
| } | ||
|
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| // CHECK-RV64-LABEL: define dso_local { <vscale x 16 x i16>, <vscale x 16 x i16> } @test_th_vlseg2e16_v_i16m4x2 | ||
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.th.vlseg2e.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, ptr [[BASE]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP0]] | ||
| // | ||
| vint16m4x2_t test_th_vlseg2e16_v_i16m4x2(const int16_t *base, size_t vl) { | ||
| return __riscv_th_vlseg2e16_v_i16m4x2(base, vl); | ||
| } | ||
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| // CHECK-RV64-LABEL: define dso_local { <vscale x 4 x i16>, <vscale x 4 x i16> } @test_th_vlseg2e16_v_u16m1x2 | ||
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.th.vlseg2e.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> poison, ptr [[BASE]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]] | ||
| // | ||
| vuint16m1x2_t test_th_vlseg2e16_v_u16m1x2(const uint16_t *base, size_t vl) { | ||
| return __riscv_th_vlseg2e16_v_u16m1x2(base, vl); | ||
| } | ||
|
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| // CHECK-RV64-LABEL: define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_th_vlseg2e16_v_u16m2x2 | ||
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.th.vlseg2e.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> poison, ptr [[BASE]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]] | ||
| // | ||
| vuint16m2x2_t test_th_vlseg2e16_v_u16m2x2(const uint16_t *base, size_t vl) { | ||
| return __riscv_th_vlseg2e16_v_u16m2x2(base, vl); | ||
| } | ||
|
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| // CHECK-RV64-LABEL: define dso_local { <vscale x 16 x i16>, <vscale x 16 x i16> } @test_th_vlseg2e16_v_u16m4x2 | ||
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.th.vlseg2e.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, ptr [[BASE]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP0]] | ||
| // | ||
| vuint16m4x2_t test_th_vlseg2e16_v_u16m4x2(const uint16_t *base, size_t vl) { | ||
| return __riscv_th_vlseg2e16_v_u16m4x2(base, vl); | ||
| } |
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