VHDL implementation of my RRISC CPU
>>> Read all about it here: https://renerocksai.github.io/rrisc <<<
The code is organized as follows:
- asm - contains the assembler and both simtest.asm and testalu.asm which are used for first tests of the CPU
- ghdl - contains the -> ghdl testbench scripts: make and run tests
- project_2.srcs - contains the VHDL CPU and testbench sources. It's in Vivado style folders. But free ghdl can be used for simulations, Vivado is only required for programming your FPGA.