A virtual RISC V emulator designed with the help of Arrvindh Shriraman
This emulator runs instructions written in the RISC V style on processors with different architectures. This was an assignment assigned by Arrvindh Shriraman for CMPT 295 - Introduction to Computer Systems and is implemented in C. I implemented most of the functions that decoded the instructions, while the test cases and supporting files were made by the professor. My main focus was a subset of the RISC V ISA to further improve my understanding of instruction set architectures I learned a lot about computer architectures and processors as well as low-level instruction processing and improved my coding skills in C