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All of my projects are available here
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You can reach me at aqusay06@gmail.com
All of my projects are available here
You can reach me at aqusay06@gmail.com
Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.
Verilog 7
JavaFX application implementing Dijkstra's algorithm for shortest path visualization in GIS maps.
Java 6