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All of my projects are available here
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You can reach me at aqusay06@gmail.com
All of my projects are available here
You can reach me at aqusay06@gmail.com
Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.
Verilog 14
Efficient Huffman Coding implementation for file compression and decompression.
JavaFX application implementing Dijkstra's algorithm for shortest path visualization in GIS maps.
C implementations of essential data structures for efficient programming solutions.
C 7
Shortest path finder using Dijkstra's algorithm for graph traversal.
C 6