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Fix Verilator guard statements in new modules
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Luca Rufer committed Jan 24, 2023
1 parent 3890cb9 commit 8095cd5
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Showing 2 changed files with 7 additions and 1 deletion.
2 changes: 1 addition & 1 deletion rtl/dmr/DMR_write_mux.sv
Original file line number Diff line number Diff line change
Expand Up @@ -78,4 +78,4 @@ for (genvar i = 0; i < NumDataItems; i++) begin
assign data_o[i] = wen[i] ? wdata_expanded[i] : data_i[i];
end

endmodule
endmodule
6 changes: 6 additions & 0 deletions test/dmr/dmr_handshake.sv
Original file line number Diff line number Diff line change
Expand Up @@ -79,6 +79,8 @@ module handshake_source #(
end
end

`ifndef VERILATOR
// pragma translate_off
// Warnings
assert property (@(posedge clk_i) disable iff (~rst_ni)
( data_q != 0 |-> data_d != 0)) else
Expand All @@ -101,6 +103,10 @@ module handshake_source #(
assert property (@(posedge clk_i) disable iff (~rst_ni)
(~ready_i & valid_o ) |=> $stable(data_o)) else
$error("[Handshake Source] data changed before handshake completed.");

// pragma translate_on
`endif

endmodule

module handshake_sink #(
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