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Cleanup
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Andrea Belano committed Jan 16, 2025
1 parent 2f010aa commit d7a555a
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1 change: 0 additions & 1 deletion Bender.yml
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Expand Up @@ -73,7 +73,6 @@ sources:
- rtl/cluster_peripherals.sv
- rtl/data_periph_demux.sv
- rtl/core_demux_wrap.sv
# Level 2
- rtl/core_region.sv
- target: simulation
files:
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1 change: 0 additions & 1 deletion Makefile
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Expand Up @@ -23,7 +23,6 @@ bender_defs += -D FEATURE_ICACHE_STAT
bender_defs += -D PRIVATE_ICACHE
bender_defs += -D HIERARCHY_ICACHE_32BIT
bender_defs += -D ICAHE_USE_FF
bender_defs += -D NO_FPU
bender_defs += -D TRACE_EXECUTION
bender_defs += -D CLUSTER_ALIAS
bender_defs += -D USE_PULP_PARAMETERS
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32 changes: 16 additions & 16 deletions packages/pulp_cluster_package.sv
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Expand Up @@ -37,7 +37,7 @@ package pulp_cluster_package;
SOFTEX
} hwpe_type_e;

parameter MAX_NUM_HWPES = 8;
localparam int unsigned MAX_NUM_HWPES = 8;

typedef struct packed {
hwpe_type_e [MAX_NUM_HWPES-1:0] HwpeList;
Expand Down Expand Up @@ -154,26 +154,26 @@ package pulp_cluster_package;
bit EnableRemapAddress;
} pulp_cluster_cfg_t;

parameter int unsigned NB_SPERIPH_PLUGS_EU = 2;
localparam int unsigned NB_SPERIPH_PLUGS_EU = 2;

// number of master and slave cluster periphs
parameter int unsigned NB_MPERIPHS = 1;
parameter int unsigned NB_SPERIPHS = 12;
localparam int unsigned NB_MPERIPHS = 1;
localparam int unsigned NB_SPERIPHS = 12;

// position of peripherals on slave port of periph interconnect
parameter int unsigned SPER_EOC_ID = 0; // 0x0000 - 0x0400
parameter int unsigned SPER_TIMER_ID = 1; // 0x0400 - 0x0800
parameter int unsigned SPER_EVENT_U_ID = 2; // 0x0800 - 0x1000
localparam int unsigned SPER_EOC_ID = 0; // 0x0000 - 0x0400
localparam int unsigned SPER_TIMER_ID = 1; // 0x0400 - 0x0800
localparam int unsigned SPER_EVENT_U_ID = 2; // 0x0800 - 0x1000
// 3 also used for Event Unit
parameter int unsigned SPER_HWPE_ID = 4; // 0x1000 - 0x1400
parameter int unsigned SPER_ICACHE_CTRL = 5; // 0x1400 - 0x1800
parameter int unsigned SPER_DMA_CL_ID = 6; // 0x1800 - 0x1C00
parameter int unsigned SPER_DMA_FC_ID = 7; // 0x1C00 - 0x2000
parameter int unsigned SPER_HMR_UNIT_ID = 8; // 0x2000 - 0x2400
parameter int unsigned SPER_TCDM_SCRUBBER_ID = 9; // 0x2400 - 0x2800
parameter int unsigned SPER_HWPE_HCI_ECC_ID = 10; // 0x2800 - 0x3200
parameter int unsigned SPER_EXT_ID = 11; // -> unmapped, directed to error
parameter int unsigned SPER_ERROR_ID = 12; // -> unmapped, directed to error
localparam int unsigned SPER_HWPE_ID = 4; // 0x1000 - 0x1400
localparam int unsigned SPER_ICACHE_CTRL = 5; // 0x1400 - 0x1800
localparam int unsigned SPER_DMA_CL_ID = 6; // 0x1800 - 0x1C00
localparam int unsigned SPER_DMA_FC_ID = 7; // 0x1C00 - 0x2000
localparam int unsigned SPER_HMR_UNIT_ID = 8; // 0x2000 - 0x2400
localparam int unsigned SPER_TCDM_SCRUBBER_ID = 9; // 0x2400 - 0x2800
localparam int unsigned SPER_HWPE_HCI_ECC_ID = 10; // 0x2800 - 0x3200
localparam int unsigned SPER_EXT_ID = 11; // -> unmapped, directed to error
localparam int unsigned SPER_ERROR_ID = 12; // -> unmapped, directed to error

// The following parameters refer to the cluster AXI crossbar
localparam byte_t NumAxiSubordinatePorts = 4;
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9 changes: 2 additions & 7 deletions rtl/cluster_bus_wrap.sv
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Expand Up @@ -72,17 +72,12 @@ module cluster_bus_wrap
input master_resp_t ext_master_resp_i
);

//`AXI_TYPEDEF_ALL_CT(xbar_slv, xbar_slv_req_t, xbar_slv_rsp_t, axi_aw_t, axi_slv_iw_t, axi_dw_t, axi_strbw_t, axi_uw_t)
//`AXI_TYPEDEF_ALL_CT(xbar_mst, xbar_mst_req_t, xbar_mst_rsp_t, axi_aw_t, axi_mst_iw_t, axi_dw_t, axi_strbw_t, axi_uw_t)

//Ensure that AXI_ID out width has the correct size with an elaboration system task
if (AXI_ID_OUT_WIDTH < AXI_ID_IN_WIDTH + $clog2(NB_SLAVE))
$error("ID width of AXI output ports is to small. The output id width must be input ID width + clog2(<nr slave ports>) which is %d but it was %d", AXI_ID_IN_WIDTH + $clog2(NB_SLAVE), AXI_ID_OUT_WIDTH);
else if (AXI_ID_OUT_WIDTH > AXI_ID_IN_WIDTH + $clog2(NB_SLAVE))
$warning("ID width of the AXI output port has the wrong length. It is larger than the required value. Trim it to the right length to get rid of this warning.");

// if (AXI_ADDR_WIDTH != 48)
// $fatal(1,"Address map is only defined for 48-bit addresses!");
if (TCDM_SIZE == 0)
$fatal(1,"TCDM size must be non-zero!");
if (TCDM_SIZE >2048*1024) // Periph start address is at offset 0x0020_0000, which actually allows for up to 2 MiB of TCDM,
Expand All @@ -93,7 +88,7 @@ module cluster_bus_wrap
slave_req_t [NB_SLAVE-1:0] axi_slave_reqs;
slave_resp_t [NB_SLAVE-1:0] axi_slave_resps;

// assign here your axi slaves
// assign here your axi slaves
`AXI_ASSIGN_REQ_STRUCT(axi_slave_reqs[0], data_slave_req_i)
`AXI_ASSIGN_RESP_STRUCT(data_slave_resp_o, axi_slave_resps[0])
`AXI_ASSIGN_REQ_STRUCT(axi_slave_reqs[1], instr_slave_req_i)
Expand All @@ -106,7 +101,7 @@ module cluster_bus_wrap
master_req_t [NB_MASTER-1:0] axi_master_reqs;
master_resp_t [NB_MASTER-1:0] axi_master_resps;

// assign here your axi masters
// assign here your axi masters
`AXI_ASSIGN_REQ_STRUCT(tcdm_master_req_o, axi_master_reqs[0])
`AXI_ASSIGN_RESP_STRUCT(axi_master_resps[0], tcdm_master_resp_i)
`AXI_ASSIGN_REQ_STRUCT(periph_master_req_o, axi_master_reqs[1])
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43 changes: 22 additions & 21 deletions rtl/cluster_interconnect_wrap.sv
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Expand Up @@ -20,32 +20,32 @@ import hci_package::*;

module cluster_interconnect_wrap
#(
parameter NB_CORES = 8,
parameter HWPE_PRESENT = 1,
parameter NB_HWPE_PORTS = 9,
parameter NB_DMAS = 4,
parameter NB_MPERIPHS = 1,
parameter NB_TCDM_BANKS = 16,
parameter NB_SPERIPHS = 10, //differ

parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
parameter BE_WIDTH = DATA_WIDTH/8,
parameter int unsigned NB_CORES = 8,
parameter int unsigned HWPE_PRESENT = 1,
parameter int unsigned NB_HWPE_PORTS = 9,
parameter int unsigned NB_DMAS = 4,
parameter int unsigned NB_MPERIPHS = 1,
parameter int unsigned NB_TCDM_BANKS = 16,
parameter int unsigned NB_SPERIPHS = 10, //differ

parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned ADDR_WIDTH = 32,
parameter int unsigned BE_WIDTH = DATA_WIDTH/8,
parameter logic [ADDR_WIDTH-1:0] ClusterBaseAddr = 'h10000000,
parameter logic [ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000,
parameter logic [ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000,

//TCDM PARAMETERS
parameter TEST_SET_BIT = 20,
parameter ADDR_MEM_WIDTH = 11,
parameter LOG_CLUSTER = 5,
parameter PE_ROUTING_LSB = 10,
parameter PE_ROUTING_MSB = PE_ROUTING_LSB+$clog2(NB_SPERIPHS)-1, //differ
parameter CLUSTER_ALIAS = 1,
parameter CLUSTER_ALIAS_BASE = 12'h000,

parameter USE_HETEROGENEOUS_INTERCONNECT = 1,
parameter USE_ECC_INTERCONNECT = 0,
parameter int unsigned TEST_SET_BIT = 20,
parameter int unsigned ADDR_MEM_WIDTH = 11,
parameter int unsigned LOG_CLUSTER = 5,
parameter int unsigned PE_ROUTING_LSB = 10,
parameter int unsigned PE_ROUTING_MSB = PE_ROUTING_LSB+$clog2(NB_SPERIPHS)-1, //differ
parameter int unsigned CLUSTER_ALIAS = 1,
parameter int unsigned CLUSTER_ALIAS_BASE = 12'h000,

parameter int unsigned USE_HETEROGENEOUS_INTERCONNECT = 1,
parameter int unsigned USE_ECC_INTERCONNECT = 0,
parameter hci_package::hci_size_parameter_t HCI_CORE_SIZE = '0,
parameter hci_package::hci_size_parameter_t HCI_HWPE_SIZE = '0,
parameter hci_package::hci_size_parameter_t HCI_MEM_SIZE = '0
Expand Down Expand Up @@ -85,6 +85,7 @@ module cluster_interconnect_wrap
.N_MEM ( NB_TCDM_BANKS ),
.IW ( TCDM_ID_WIDTH ),
.TS_BIT ( TEST_SET_BIT ),
//For an explanation of these macros refer to https://github.com/pulp-platform/hci/blob/v2.1.1/rtl/common/hci_helpers.svh
.`HCI_SIZE_PARAM(cores) ( HCI_CORE_SIZE ),
.`HCI_SIZE_PARAM(mems) ( HCI_MEM_SIZE ),
.`HCI_SIZE_PARAM(hwpe) ( HCI_HWPE_SIZE )
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28 changes: 14 additions & 14 deletions rtl/cluster_peripherals.sv
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Expand Up @@ -21,19 +21,19 @@
module cluster_peripherals
import pulp_cluster_package::*;
#(
parameter NB_CORES = 8,
parameter NB_HWPES = 8,
parameter NB_MPERIPHS = 1,
parameter NB_CACHE_BANKS = 4,
parameter NB_SPERIPHS = 8,
parameter NB_TCDM_BANKS = 8,
parameter ROM_BOOT_ADDR = 32'h1A000000,
parameter BOOT_ADDR = 32'h1C000000,
parameter EVNT_WIDTH = 8,
parameter FEATURE_DEMUX_MAPPED = 1,
parameter int unsigned NB_L1_CUTS = 16,
parameter int unsigned RW_MARGIN_WIDTH = 4,
parameter int unsigned NB_BARRIERS = NB_CORES
parameter int unsigned NB_CORES = 8,
parameter int unsigned NB_HWPES = 8,
parameter int unsigned NB_MPERIPHS = 1,
parameter int unsigned NB_CACHE_BANKS = 4,
parameter int unsigned NB_SPERIPHS = 8,
parameter int unsigned NB_TCDM_BANKS = 8,
parameter int unsigned ROM_BOOT_ADDR = 32'h1A000000,
parameter int unsigned BOOT_ADDR = 32'h1C000000,
parameter int unsigned EVNT_WIDTH = 8,
parameter int unsigned FEATURE_DEMUX_MAPPED = 1,
parameter int unsigned NB_L1_CUTS = 16,
parameter int unsigned RW_MARGIN_WIDTH = 4,
parameter int unsigned NB_BARRIERS = NB_CORES
)
(
input logic clk_i,
Expand Down Expand Up @@ -109,7 +109,6 @@ module cluster_peripherals
output logic [NB_CORES-1:0] enable_l1_l15_prefetch_o,
output logic [NB_CORES-1:0] flush_valid_o,
input logic [NB_CORES-1:0] flush_ready_i,
// input snitch_icache_pkg::icache_l0_events_t [NB_CORES-1:0] l0_events_i,
input snitch_icache_pkg::icache_l1_events_t l1_events_i
);

Expand Down Expand Up @@ -286,6 +285,7 @@ module cluster_peripherals
//********************************************************

`ifdef SNITCH_ICACHE
//For an explanation of this macro refer to https://github.com/pulp-platform/register_interface/blob/master/include/register_interface/typedef.svh#L34
`REG_BUS_TYPEDEF_ALL(icache, logic[31:0], logic[31:0], logic[3:0])
icache_req_t icache_req;
icache_rsp_t icache_rsp;
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45 changes: 22 additions & 23 deletions rtl/core_region.sv
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Expand Up @@ -27,28 +27,28 @@ module core_region
import rapid_recovery_pkg::*;
#(
// CORE PARAMETERS
parameter CORE_TYPE_CL = 0, // 0 for CV32, 1 RI5CY, 2 for IBEX RV32IMC
parameter N_EXT_PERF_COUNTERS = 1,
parameter NUM_INTERRUPTS = 32,
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter INSTR_RDATA_WIDTH = 32,
parameter CLUSTER_ALIAS = 1,
parameter CLUSTER_ALIAS_BASE = 12'h000,
parameter REMAP_ADDRESS = 0,

parameter APU_NARGS_CPU = 2,
parameter APU_WOP_CPU = 1,
parameter WAPUTYPE = 3,
parameter APU_NDSFLAGS_CPU = 3,
parameter APU_NUSFLAGS_CPU = 5,

parameter FPU = 0,
parameter FP_DIVSQRT = 0,
parameter SHARED_FP = 0,
parameter SHARED_FP_DIVSQRT = 0,

parameter DEBUG_START_ADDR = 32'h1A110000,
parameter int unsigned CORE_TYPE_CL = 0, // 0 for CV32, 1 RI5CY, 2 for IBEX RV32IMC
parameter int unsigned N_EXT_PERF_COUNTERS = 1,
parameter int unsigned NUM_INTERRUPTS = 32,
parameter int unsigned ADDR_WIDTH = 32,
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned INSTR_RDATA_WIDTH = 32,
parameter int unsigned CLUSTER_ALIAS = 1,
parameter int unsigned CLUSTER_ALIAS_BASE = 12'h000,
parameter int unsigned REMAP_ADDRESS = 0,

parameter int unsigned APU_NARGS_CPU = 2,
parameter int unsigned APU_WOP_CPU = 1,
parameter int unsigned WAPUTYPE = 3,
parameter int unsigned APU_NDSFLAGS_CPU = 3,
parameter int unsigned APU_NUSFLAGS_CPU = 5,

parameter int unsigned FPU = 0,
parameter int unsigned FP_DIVSQRT = 0,
parameter int unsigned SHARED_FP = 0,
parameter int unsigned SHARED_FP_DIVSQRT = 0,

parameter int unsigned DEBUG_START_ADDR = 32'h1A110000,

parameter type core_data_req_t = logic,
parameter type core_data_rsp_t = logic,
Expand Down Expand Up @@ -114,7 +114,6 @@ import rapid_recovery_pkg::*;
input logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i
);

// localparam N_EXT_PERF_COUNTERS_ACTUAL = 5;
localparam USE_IBEX = CORE_TYPE_CL == 1 || CORE_TYPE_CL == 2;
localparam IBEX_RV32M = CORE_TYPE_CL == 1 ? ibex_pkg::RV32MSingleCycle : ibex_pkg::RV32MNone;
localparam IBEX_RV32E = CORE_TYPE_CL == 2;
Expand Down
12 changes: 6 additions & 6 deletions rtl/data_periph_demux.sv
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Expand Up @@ -17,12 +17,12 @@

module data_periph_demux
#(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter BYTE_ENABLE_BIT = DATA_WIDTH/8,
parameter REMAP_ADDRESS = 0,
parameter CLUSTER_ALIAS = 1,
parameter CLUSTER_ALIAS_BASE = 12'h000
parameter int unsigned ADDR_WIDTH = 32,
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned BYTE_ENABLE_BIT = DATA_WIDTH/8,
parameter int unsigned REMAP_ADDRESS = 0,
parameter int unsigned CLUSTER_ALIAS = 1,
parameter int unsigned CLUSTER_ALIAS_BASE = 12'h000
)
(
input logic clk,
Expand Down
7 changes: 3 additions & 4 deletions rtl/hwpe_subsystem.sv
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Expand Up @@ -15,16 +15,15 @@

`include "hci_helpers.svh"

import hci_package::*;
import pulp_cluster_package::*;

module hwpe_subsystem
import hci_package::*;
import pulp_cluster_package::*;
#(
parameter hwpe_subsystem_cfg_t HWPE_CFG = '0,
parameter int unsigned N_CORES = 8,
parameter int unsigned N_MASTER_PORT = 9,
parameter int unsigned ID_WIDTH = 8,
parameter hci_package::hci_size_parameter_t HCI_HWPE_SIZE = '0
parameter hci_package::hci_size_parameter_t HCI_HWPE_SIZE = '0
)
(
input logic clk,
Expand Down
35 changes: 2 additions & 33 deletions rtl/mchan_wrap.sv
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Expand Up @@ -38,8 +38,7 @@ module dmac_wrap
input logic clk_i,
input logic rst_ni,
input logic test_mode_i,
//FIXME: iDMA
// XBAR_TCDM_BUS.Slave ctrl_slave[NB_CORES-1:0],

hci_core_intf.target ctrl_slave[0:NB_CORES-1],
XBAR_PERIPH_BUS.Slave cl_ctrl_slave,
XBAR_PERIPH_BUS.Slave fc_ctrl_slave,
Expand Down Expand Up @@ -148,26 +147,8 @@ module dmac_wrap

mchan #(

.NB_CTRLS ( NB_CTRLS ), // NUMBER OF CONTROL PORTS : 8 CORES, CL, FC
//.NB_TRANSFERS ( 16 ), // NUMBER OF AVAILABLE DMA CHANNELS
//.CTRL_TRANS_QUEUE_DEPTH ( 2 ), // DEPTH OF PRIVATE PER-CORE COMMAND QUEUE (CTRL_UNIT)
//.GLOBAL_TRANS_QUEUE_DEPTH ( 8 ), // DEPTH OF GLOBAL COMMAND QUEUE (CTRL_UNIT)

//.TCDM_ADD_WIDTH ( TCDM_ADD_WIDTH ), // WIDTH OF TCDM ADDRESS
//.EXT_ADD_WIDTH ( 32 ), // WIDTH OF GLOBAL EXTERNAL ADDRESS
//.NB_OUTSND_TRANS ( 8 ), // NUMBER OF OUTSTANDING TRANSACTIONS
//.MCHAN_BURST_LENGTH ( 256 ), // ANY POWER OF 2 VALUE FROM 32 TO 2048

//.AXI_ADDR_WIDTH ( 32 ),
//.AXI_DATA_WIDTH ( 64 ),
//.AXI_USER_WIDTH ( 6 ),
//.AXI_ID_WIDTH ( 4 ),

//.PE_ID_WIDTH ( PE_ID_WIDTH )
//.NB_CORES ( NB_CORES ), // NUMBER OF CORES
// .NB_TRANSFERS ( 2*NB_CORES ), // FIXME: iDMA
.NB_CTRLS ( NB_CTRLS ), // NUMBER OF CONTROL PORTS : 8 CORES, CL, FC
.NB_TRANSFERS ( 16 ),
//.CORE_TRANS_QUEUE_DEPTH ( 2 ), // DEPTH OF PRIVATE PER-CORE COMMAND QUEUE (CTRL_UNIT)
.GLOBAL_TRANS_QUEUE_DEPTH ( 2*NB_CORES ), // DEPTH OF GLOBAL COMMAND QUEUE (CTRL_UNIT)
.TCDM_ADD_WIDTH ( TCDM_ADD_WIDTH ), // WIDTH OF TCDM ADDRESS
.EXT_ADD_WIDTH ( AXI_ADDR_WIDTH ), // WIDTH OF GLOBAL EXTERNAL ADDRESS
Expand All @@ -183,18 +164,6 @@ module dmac_wrap
.rst_ni ( rst_ni ),
.test_mode_i ( test_mode_i ),

//.ctrl_pe_targ_req_i ( ),
//.ctrl_pe_targ_add_i ( ),
//.ctrl_pe_targ_type_i ( ),
//.ctrl_pe_targ_be_i ( ),
//.ctrl_pe_targ_data_i ( ),
//.ctrl_pe_targ_id_i ( ),
//.ctrl_pe_targ_gnt_o ( ),
//.ctrl_pe_targ_r_valid_o ( ),
//.ctrl_pe_targ_r_data_o ( ),
//.ctrl_pe_targ_r_opc_o ( ),
//.ctrl_pe_targ_r_id_o ( ),

.ctrl_targ_req_i ( s_ctrl_bus_req ),
.ctrl_targ_add_i ( s_ctrl_bus_add ),
.ctrl_targ_type_i ( s_ctrl_bus_wen ),
Expand Down
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