Merge pull request #78 from pulp-platform/redundancy-updates

Bump redundancy cells updating SRAMs and HMR unit.
pulp-platform · Jun 25, 2024 · 7ccc1d0 · 7ccc1d0
2 parents 76d1a6d + 98f536b
commit 7ccc1d0
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Showing 7 changed files with 272 additions and 77 deletions.
diff --git a/Bender.lock b/Bender.lock
@@ -38,7 +38,7 @@ packages:
     dependencies:
     - common_cells
   cluster_icache:
-    revision: b3b0c474eb5baa2fdeece65369805206398ab63b
+    revision: 4cffcf37724704ab27d483338804a1981f5c4497
     version: null
     source:
       Git: https://github.com/pulp-platform/cluster_icache.git
@@ -116,6 +116,18 @@ packages:
     - cluster_interconnect
     - hwpe-stream
     - l2_tcdm_hybrid_interco
+  hier-icache:
+    revision: 2886cb2a46cea3e2bd2d979b505d88fadfbe150c
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/hier-icache.git
+    dependencies:
+    - axi
+    - axi_slice
+    - common_cells
+    - icache-intc
+    - scm
+    - tech_cells_generic
   hwpe-ctrl:
     revision: a5966201aeeb988d607accdc55da933a53c6a56e
     version: null
@@ -137,6 +149,12 @@ packages:
       Git: https://github.com/pulp-platform/ibex.git
     dependencies:
     - tech_cells_generic
+  icache-intc:
+    revision: 663c3b6d3c2bf63ff25cda46f33c799c647b3985
+    version: 1.0.1
+    source:
+      Git: https://github.com/pulp-platform/icache-intc.git
+    dependencies: []
   idma:
     revision: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1
     version: null
@@ -191,7 +209,7 @@ packages:
     - hwpe-stream
     - tech_cells_generic
   redundancy_cells:
-    revision: c37bdb47339bf70e8323de8df14ea8bbeafb6583
+    revision: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc
     version: null
     source:
       Git: https://github.com/pulp-platform/redundancy_cells.git
@@ -219,12 +237,11 @@ packages:
     - fpnew
     - tech_cells_generic
   scm:
-    revision: 74426dee36f28ae1c02f7635cf844a0156145320
-    version: null
+    revision: 998466d2a3c2d7d572e43d2666d93c4f767d8d60
+    version: 1.1.1
     source:
       Git: https://github.com/pulp-platform/scm.git
-    dependencies:
-    - tech_cells_generic
+    dependencies: []
   softex:
     revision: 23faeccaf204817bc9e6649e469072e5726be561
     version: 1.0.0
@@ -238,8 +255,8 @@ packages:
     - hwpe-stream
     - ibex
   tech_cells_generic:
-    revision: a9cae21902e75b1434328ecf36f85327ba5717de
-    version: 0.2.11
+    revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
+    version: 0.2.13
     source:
       Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:

diff --git a/Bender.yml b/Bender.yml
@@ -19,7 +19,8 @@ dependencies:
   event_unit_flex:        { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr
   mchan:                  { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization
   idma:                   { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master
-  cluster_icache:         { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "b3b0c474eb5baa2fdeece65369805206398ab63b" }
+  cluster_icache:         { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "4cffcf37724704ab27d483338804a1981f5c4497" } # branch: astral-synth
+  hier-icache:            { git: "https://github.com/pulp-platform/hier-icache.git", rev: "2886cb2a46cea3e2bd2d979b505d88fadfbe150c" } # branch: astral
   cluster_peripherals:    { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2
   axi:                    { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3  }
   timer_unit:             { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 }
@@ -31,7 +32,7 @@ dependencies:
   scm:                    { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating
   hci:                    { git: "https://github.com/pulp-platform/hci.git", rev: afe0220 } # branch: master
   register_interface:     { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4  }
-  redundancy_cells:       { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase
+  redundancy_cells:       { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc } # branch: astral-v0
   redmule:                { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1
   neureka:                { git: "https://github.com/pulp-platform/neureka.git", version: 1.0.0 }
   softex:                 { git: "https://github.com/belanoa/softex.git"       , version: 1.0.0 }

diff --git a/Makefile b/Makefile
@@ -39,6 +39,7 @@ bender_defs += -D NO_FPU
 bender_defs += -D TRACE_EXECUTION
 bender_defs += -D CLUSTER_ALIAS
 bender_defs += -D USE_PULP_PARAMETERS
+bender_defs += -D SNITCH_ICACHE
 
 bender_targs += -t rtl
 bender_targs += -t test

diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv
@@ -161,7 +161,7 @@ module cluster_bus_wrap
     MaxSlvTrans: DMA_NB_OUTSND_BURSTS + NB_CORES,       //Allow up to 4 in-flight transactions
     //per slave port
     FallThrough: 1'b0,       //Use the reccomended default config 
-    LatencyMode: axi_pkg::NO_LATENCY, // CUT_ALL_AX | axi_pkg::DemuxW,
+    LatencyMode: axi_pkg::CUT_ALL_AX, // CUT_ALL_AX | axi_pkg::DemuxW,
     PipelineStages: 0,
     AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH,
     AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH,

diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv
@@ -105,7 +105,9 @@ module cluster_peripherals
   output hci_package::hci_interconnect_ctrl_t hci_ctrl_o,
 
   // Control ports
-  output logic                         enable_l1_l15_prefetch_o,
+  SP_ICACHE_CTRL_UNIT_BUS.Master       IC_ctrl_unit_bus_main[NB_CACHE_BANKS-1:0],
+  PRI_ICACHE_CTRL_UNIT_BUS.Master      IC_ctrl_unit_bus_pri[NB_CORES-1:0],
+  output logic [NB_CORES-1:0]          enable_l1_l15_prefetch_o,
   output logic [NB_CORES-1:0]          flush_valid_o,
   input  logic [NB_CORES-1:0]          flush_ready_i,
   // input  snitch_icache_pkg::icache_l0_events_t [NB_CORES-1:0] l0_events_i,
@@ -284,6 +286,7 @@ module cluster_peripherals
   //******************** icache_ctrl_unit ******************
   //********************************************************
 
+`ifdef SNITCH_ICACHE
   `REG_BUS_TYPEDEF_ALL(icache, logic[31:0], logic[31:0], logic[3:0])
   icache_req_t icache_req;
   icache_rsp_t icache_rsp;
@@ -326,14 +329,56 @@ module cluster_peripherals
     .reg_req_i            ( icache_req ),
     .reg_rsp_o            ( icache_rsp ),
 
-    .enable_prefetching_o ( enable_l1_l15_prefetch_o),
+    .enable_prefetching_o ( enable_l1_l15_prefetch_o[0]),
     .flush_valid_o,
     .flush_ready_i,
 
     // .l0_events_i,
     .l1_events_i
   );
 
+  assign enable_l1_l15_prefetch_o[NB_CORES-1:1] = '0;
+
+  for (genvar i = 0; i < NB_CORES; i++) begin
+    assign IC_ctrl_unit_bus_pri[i].bypass_req     = '0;
+    assign IC_ctrl_unit_bus_pri[i].flush_req      = '0;
+    assign IC_ctrl_unit_bus_pri[i].sel_flush_req  = '0;
+    assign IC_ctrl_unit_bus_pri[i].sel_flush_addr = '0;
+    `ifdef FEATURE_ICACHE_STAT
+      assign IC_ctrl_unit_bus_pri[i].ctrl_clear_regs  = '0;
+      assign IC_ctrl_unit_bus_pri[i].ctrl_enable_regs = '0;
+    `endif
+  end
+
+  for (genvar i = 0; i < NB_CACHE_BANKS; i++) begin
+    assign IC_ctrl_unit_bus_main[i].ctrl_req_enable   = '0;
+    assign IC_ctrl_unit_bus_main[i].ctrl_req_disable  = '0;
+    assign IC_ctrl_unit_bus_main[i].ctrl_flush_req    = '0;
+    assign IC_ctrl_unit_bus_main[i].icache_is_private = '0;
+    assign IC_ctrl_unit_bus_main[i].sel_flush_req     = '0;
+    assign IC_ctrl_unit_bus_main[i].sel_flush_addr    = '0;
+    `ifdef FEATURE_ICACHE_STAT
+      assign IC_ctrl_unit_bus_main[i].ctrl_clear_regs  = '0;
+      assign IC_ctrl_unit_bus_main[i].ctrl_enable_regs = '0;
+    `endif
+  end
+`else
+  assign flush_valid_o = '0;
+  hier_icache_ctrl_unit_wrap #(
+    .NB_CACHE_BANKS ( NB_CACHE_BANKS       ),
+    .NB_CORES       ( NB_CORES             ),
+    .ID_WIDTH       ( NB_CORES+NB_MPERIPHS )
+  ) icache_ctrl_unit_i (
+    .clk_i                       (  clk_i                           ),
+    .rst_ni                      (  rst_ni                          ),
+
+    .speriph_slave               (  speriph_slave[SPER_ICACHE_CTRL] ),
+    .IC_ctrl_unit_bus_pri        (  IC_ctrl_unit_bus_pri            ),
+    .IC_ctrl_unit_bus_main       (  IC_ctrl_unit_bus_main           ),
+    .enable_l1_l15_prefetch_o    (  enable_l1_l15_prefetch_o        )
+  );
+`endif
+
   //********************************************************
   //******************** DMA CL CONFIG PORT ****************
   //********************************************************