Merge pull request #23 from pulp-platform/control_pulp_dev

Add cv32e40p support for pulpissimo, pulp and control-pulp

configs/pulp_cv32e40p.sh

@@ -0,0 +1,16 @@
+#!/bin/bash -e
+
+export PULPRT_TARGET=pulp
+export PULPRUN_TARGET=pulp
+export USE_CV32E40P=1
+
+if [  -n "${ZSH_VERSION:-}" ]; then 
+        DIR="$(readlink -f -- "${(%):-%x}")"
+        scriptDir="$(dirname $DIR)"
+else
+
+    scriptDir="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")"
+
+fi
+
+source $scriptDir/common.sh

configs/pulpissimo.sh

@@ -3,7 +3,7 @@
 export PULPRT_TARGET=pulpissimo
 export PULPRUN_TARGET=pulpissimo
 
-if [  -n "${ZSH_VERSION:-}" ]; then 
+if [  -n "${ZSH_VERSION:-}" ]; then
         DIR="$(readlink -f -- "${(%):-%x}")"
         scriptDir="$(dirname $DIR)"
 else

configs/pulpissimo_cv32e40p.sh

@@ -0,0 +1,16 @@
+#!/bin/bash -e
+
+export PULPRT_TARGET=pulpissimo
+export PULPRUN_TARGET=pulpissimo
+export USE_CV32E40P=1
+
+if [  -n "${ZSH_VERSION:-}" ]; then
+        DIR="$(readlink -f -- "${(%):-%x}")"
+        scriptDir="$(dirname $DIR)"
+else
+
+    scriptDir="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")"
+
+fi
+
+source $scriptDir/common.sh

include/archi/chips/control-pulp/pulp.h

@@ -23,10 +23,17 @@
 
 #include "archi/itc/itc_v1.h"
 
+// cv32e40p-specific
+#include "archi/cv32e40p/cv32e40p.h"
+#include "archi/riscv/priv_1_11.h"
+
 #include "archi/chips/control-pulp/memory_map.h"
 #include "archi/chips/control-pulp/apb_soc.h"
+#include "archi/stdout/stdout_v3.h"
+#include "archi/dma/mchan_v7.h"
 
 #include "archi/udma/spim/udma_spim_v3.h"
+#include "archi/udma/i2c/udma_i2c_v2.h"
 #include "archi/udma/uart/udma_uart_v1.h"
 #include "archi/udma/udma_v3.h"
 

include/archi/chips/pulp/pulp.h

@@ -22,13 +22,17 @@
 #include "archi/chips/pulp/apb_soc_ctrl.h"
 
 #include "archi/gpio/gpio_v3.h"
-#include "archi/riscv/priv_1_10.h"
 #ifdef __ibex__
 #include "archi/ibex/mhpm.h"
-#else // __ibex__
+#elif defined(__cv32e40p__)
+#include "archi/cv32e40p/cv32e40p.h"
+#include "archi/riscv/priv_1_11.h"
+#else
 #include "archi/riscv/pcer_v2.h"
+#include "archi/riscv/priv_1_10.h"
 #endif // __ibex__
 #include "archi/itc/itc_v1.h"
+#include "archi/riscv/priv_1_10.h"
 
 #include "archi/chips/pulp/memory_map.h"
 #include "archi/chips/pulp/apb_soc.h"

include/archi/chips/pulpissimo/pulp.h

@@ -23,11 +23,15 @@
 
 //#include "archi/periph_v2.h"
 #include "archi/gpio/gpio_v3.h"
-#include "archi/riscv/priv_1_10.h"
 #ifdef __ibex__
 #include "archi/ibex/mhpm.h"
-#else // __ibex__
+#include "archi/riscv/priv_1_10.h"
+#elif defined(__cv32e40p__)
+#include "archi/cv32e40p/cv32e40p.h"
+#include "archi/riscv/priv_1_11.h"
+#else
 #include "archi/riscv/pcer_v2.h"
+#include "archi/riscv/priv_1_10.h"
 #endif // __ibex__
 
 #include "archi/chips/pulpissimo/memory_map.h"
@@ -40,4 +44,4 @@
 #include "archi/udma/uart/udma_uart_v1.h"
 #include "archi/udma/udma_v3.h"
 
-#endif
+#endif

include/archi/cv32e40p/cv32e40p.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2018 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+/*
+ * Bit definitions for Performance counters mode registers
+ *
+ */
+#define CSR_PCER_CYCLES        0  /* Count the number of cycles the core was running */
+#define CSR_PCER_INSTR         1  /* Count the number of instructions executed */
+#define CSR_PCER_LD_STALL      2  /* Number of load use hazards */
+#define CSR_PCER_JMP_STALL     3  /* Number of jump register hazards */
+#define CSR_PCER_IMISS         4  /* Cycles waiting for instruction fetches. i.e. the number of instructions wasted due to non-ideal caches */
+#define CSR_PCER_LD            5  /* Number of memory loads executed. Misaligned accesses are counted twice */
+#define CSR_PCER_ST            6  /* Number of memory stores executed. Misaligned accesses are counted twice */
+#define CSR_PCER_JUMP          7  /* Number of jump instructions seen, i.e. j, jr, jal, jalr */
+#define CSR_PCER_BRANCH        8  /* Number of branch instructions seen, i.e. bf, bnf */
+#define CSR_PCER_TAKEN_BRANCH  9  /* Number of taken branch instructions seen, i.e. bf, bnf */
+#define CSR_PCER_COMP_INSTR   10  /* Number of compressed instructions */
+#define CSR_PCER_PIPE_STALL   11  /* Cycles wasted due to ELW instruction */
+#define CSR_PCER_APU_TYPE     12  /* Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */
+#define CSR_PCER_APU_CONT     13  /* Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */
+#define CSR_PCER_APU_DEP      14  /* Cycles used for memory loads to EXT. Every non-TCDM access is considered external */
+#define CSR_PCER_APU_WB       15  /* Cycles used for memory stores to EXT. Every non-TCDM access is considered external */
+
+
+// Gives from the event ID, the HW mask that can be stored (with an OR with other events mask) to the PCER
+#define CSR_PCER_EVENT_MASK(eventId)  (1<<(eventId))
+#define CSR_PCER_ALL_EVENTS_MASK  0xffffffff
+
+#define CSR_PCMR_ACTIVE           0x1 /* Activate counting */
+#define CSR_PCMR_SATURATE         0x2 /* Activate saturation */
+
+#define CSR_PCER_NAME(id) \
+    ( id == 0 ? "Cycles" : \
+      id == 1 ? "Instructions" : \
+      id == 2 ? "LD_Stall" : \
+      id == 3 ? "Jmp_Stall" : \
+      id == 4 ? "IMISS" : \
+      id == 5 ? "LD" : \
+      id == 6 ? "ST" : \
+      id == 7 ? "JUMP" : \
+      id == 8 ? "BRANCH" : \
+      id == 9 ? "TAKEN_BRANCH" : \
+      id == 10 ? "COMP_INSTR" : \
+      id == 11 ? "PIPE_STALL" : \
+      id == 12 ? "APU_TYPE" : \
+      id == 13 ? "APU_CONT" : \
+      id == 14 ? "APU_DEP" : \
+      id == 15 ? "APU_WB" : \
+      "NA")

include/archi/riscv/priv_1_11.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2018 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARCHI_RISCV_PRIV_1_9_H
+#define _ARCHI_RISCV_PRIV_1_9_H
+
+#define RV_CSR_MSTATUS  0x300
+#define RV_CSR_MEPC     0x341
+#define RV_CSR_MCAUSE   0x342
+#define RV_CSR_MTVAL    0x343
+#define RV_CSR_MESTATUS 0x7C0
+#ifdef RISCV_1_7
+#define RV_CSR_MCPUID   0xF00
+#define RV_CSR_MIMPID   0xF01
+#define RV_CSR_MHARTID  0xF10
+#else
+#define RV_CSR_MISA     0xF10
+#define RV_CSR_MIMPID   0xF13
+#define RV_CSR_MHARTID  0xF14
+#endif
+
+#define CSR_PCCR(N)	(0x780 + (N))
+#define CSR_PCER	0xCC0
+#define CSR_PCMR	0xCC1
+
+#define CSR_STACK_CONF   0x7D0
+#define CSR_STACK_START  0x7D1
+#define CSR_STACK_END    0x7D2
+
+#define CSR_MESTATUS_INTEN_BIT 0
+#define CSR_MESTATUS_PRV_BIT   1
+
+#define CSR_MESTATUS_PRV_MACH  3
+
+#define CSR_HWLOOP0_START   0x800
+#define CSR_HWLOOP0_END     0x801
+#define CSR_HWLOOP0_COUNTER 0x802
+#define CSR_HWLOOP1_START   0x804
+#define CSR_HWLOOP1_END     0x805
+#define CSR_HWLOOP1_COUNTER 0x806
+
+#endif

include/bench/bench.h

@@ -145,6 +145,8 @@ static inline void perf_start(void) {
   cpu_perf_conf(CSR_PCMR_ACTIVE | CSR_PCMR_SATURATE);
 #elif defined(__ibex__)
   cpu_perf_start();
+#elif defined(__cv32e40p__)
+  cpu_perf_start();
 #else
   cpu_perf_conf_events(SPR_PCER_ALL_EVENTS_MASK);
   cpu_perf_conf(SPR_PCMR_ACTIVE | SPR_PCMR_SATURATE);
@@ -177,6 +179,8 @@ static inline void perf_reset(void) {
   perf_stop();
   cpu_perf_setall(0);
   perf_start();
+#elif defined(__cv32e40p__)
+  cpu_perf_setall(0xffffffff);
 #endif
   // TODO this is failing on most targets, please include that also for specific ones
 #if 0
@@ -194,6 +198,8 @@ static inline void perf_enable_id( int eventid){
   cpu_perf_conf(CSR_PCMR_ACTIVE | CSR_PCMR_SATURATE);
 #elif defined(__ibex__)
   cpu_perf_conf_events(CSR_PCER_EVENT_MASK(eventid));
+#elif defined(__cv32e40p__)
+  cpu_perf_conf_events(1<<eventid);
 #else
   cpu_perf_conf_events(SPR_PCER_EVENT_MASK(eventid));
   cpu_perf_conf(SPR_PCMR_ACTIVE | SPR_PCMR_SATURATE);
@@ -217,13 +223,13 @@ static inline void plp_power_init() {
 
 static inline void plp_power_start() {
 #if PULP_CHIP == CHIP_PULP4
-	set_gpio_pin_value(PIN_CAM_I2S_SDI1+1, 1);
+  set_gpio_pin_value(PIN_CAM_I2S_SDI1+1, 1);
 #endif
 }
 
 static inline void plp_power_stop() {
 #if PULP_CHIP == CHIP_PULP4
-	set_gpio_pin_value(PIN_CAM_I2S_SDI1+1, 0);
+  set_gpio_pin_value(PIN_CAM_I2S_SDI1+1, 0);
 #endif
 }
 

include/hal/chips/control-pulp/pulp.h

@@ -17,7 +17,9 @@
 #ifndef __HAL_CHIPS_CONTROL_PULP_H__
 #define __HAL_CHIPS_CONTROL_PULP_H__
 
-#include "hal/riscv/riscv_v5.h"
+// cv32e40p-specific
+#include "hal/cv32e40p/cv32e40p.h"
+
 #include "hal/eu/eu_v3.h"
 #include "hal/itc/itc_v1.h"
 #include "hal/dma/mchan_v7.h"

include/hal/chips/pulp/pulp.h

@@ -19,7 +19,9 @@
 
 #ifdef __ibex__
 #include "hal/ibex/ibex.h"
-#else // __ibex__
+#elif defined(__cv32e40p__)
+#include "hal/cv32e40p/cv32e40p.h"
+#else
 #include "hal/riscv/riscv_v5.h"
 #endif // __ibex__
 #include "hal/eu/eu_v3.h"

include/hal/chips/pulpissimo/pulp.h

@@ -19,7 +19,9 @@
 
 #ifdef __ibex__
 #include "hal/ibex/ibex.h"
-#else // __ibex__
+#elif defined(__cv32e40p__)
+#include "hal/cv32e40p/cv32e40p.h"
+#else
 #include "hal/riscv/riscv_v5.h"
 #endif // __ibex__
 #include "hal/itc/itc_v1.h"
@@ -37,4 +39,4 @@
 #include "hal/udma/spim/udma_spim_v3.h"
 #include "hal/udma/uart/udma_uart_v1.h"
 
-#endif
+#endif