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frontend: fix obi_demux and addr decode #345

frontend: fix obi_demux and addr decode

frontend: fix obi_demux and addr decode #345

GitHub Actions / verible-verilog-lint failed Feb 4, 2025 in 0s

reviewdog [verible-verilog-lint] report

reported by reviewdog 🐶

Findings (10)

src/frontend/inst64/idma_inst64_top.sv|151 col 56| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
src/frontend/inst64/idma_inst64_top.sv|256 col 54| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
src/frontend/inst64/idma_inst64_top.sv|291 col 11| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
src/frontend/inst64/idma_inst64_top.sv|292 col 1| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
src/frontend/inst64/idma_inst64_top.sv|295 col 33| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
src/frontend/inst64/idma_inst64_top.sv|581 col 39| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
src/frontend/inst64/idma_inst64_top.sv|600 col 21| Explicitly define a default case for every case statement or add unique qualifier to the case statement. [Style: case-statements] [case-missing-default]
src/frontend/inst64/idma_inst64_top.sv|698 col 1| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
src/frontend/inst64/idma_inst64_top.sv|719 col 12| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
src/frontend/inst64/idma_inst64_top.sv|720 col 1| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

Filtered Findings (0)

Annotations

Check warning on line 151 in src/frontend/inst64/idma_inst64_top.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L151

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/frontend/inst64/idma_inst64_top.sv" range:{start:{line:151 column:56}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:151 column:56} end:{line:152}} text:"    logic     [NumChannels-1:0] obi_we_q,     obi_we_d;\n"}

Check warning on line 256 in src/frontend/inst64/idma_inst64_top.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L256

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/frontend/inst64/idma_inst64_top.sv" range:{start:{line:256 column:54}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:256 column:54} end:{line:257}} text:"            .axi_write_req_o  ( axi_write_req  [c] ),\n"}

Check warning on line 291 in src/frontend/inst64/idma_inst64_top.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L291

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/frontend/inst64/idma_inst64_top.sv" range:{start:{line:291 column:11}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:291 column:11} end:{line:294}} text:"        );\n\n        // OBI mux read or write\n"}

Check warning on line 292 in src/frontend/inst64/idma_inst64_top.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L292

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/frontend/inst64/idma_inst64_top.sv" range:{start:{line:292 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

Check warning on line 295 in src/frontend/inst64/idma_inst64_top.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L295

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/frontend/inst64/idma_inst64_top.sv" range:{start:{line:295 column:33}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

Check warning on line 581 in src/frontend/inst64/idma_inst64_top.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L581

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/frontend/inst64/idma_inst64_top.sv" range:{start:{line:581 column:39}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:581 column:39} end:{line:582}} text:"                // use init for memset\n"}

Check warning on line 600 in src/frontend/inst64/idma_inst64_top.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L600

Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]
Raw output
message:"Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]" location:{path:"src/frontend/inst64/idma_inst64_top.sv" range:{start:{line:600 column:21}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

Check warning on line 698 in src/frontend/inst64/idma_inst64_top.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L698

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/frontend/inst64/idma_inst64_top.sv" range:{start:{line:698 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:698 column:1} end:{line:699}} text:"\n"}

Check warning on line 719 in src/frontend/inst64/idma_inst64_top.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L719

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/frontend/inst64/idma_inst64_top.sv" range:{start:{line:719 column:12}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:719 column:12} end:{line:721}} text:"        end\n\n"}

Check warning on line 720 in src/frontend/inst64/idma_inst64_top.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L720

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/frontend/inst64/idma_inst64_top.sv" range:{start:{line:720 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}