Add support for zquarterinx extensions

pulp-platform · Oct 16, 2024 · 13b8f41 · 13b8f41
1 parent eb7f513
commit 13b8f41
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Showing 2 changed files with 17 additions and 2 deletions.
diff --git a/src/riscv.rs b/src/riscv.rs
@@ -3382,7 +3382,7 @@ pub fn parse_u32(raw: u32) -> Format {
         0xe4001053 => return parse_rd_rs1(OpcodeRdRs1::FclassH, raw),
         0xf4000053 => return parse_rd_rs1(OpcodeRdRs1::FmvHX, raw),
         0x42200053 => return parse_rd_rs1(OpcodeRdRs1::FcvtDH, raw),
-        0x44300053 => return parse_rd_rs1(OpcodeRdRs1::FcvtHB, raw),
+        0x44307053 => return parse_rd_rs1(OpcodeRdRs1::FcvtHB, raw),
         0x46300053 => return parse_rd_rs1(OpcodeRdRs1::FcvtBB, raw),
         0x8e000033 => return parse_rd_rs1(OpcodeRdRs1::VfsqrtS, raw),
         0x98100033 => return parse_rd_rs1(OpcodeRdRs1::VfclassS, raw),

diff --git a/src/tran.rs b/src/tran.rs
@@ -3631,6 +3631,9 @@ impl<'a> InstructionTranslator<'a> {
         // Encode the operation
         let op_value: u8 = std::mem::transmute(op as u8);
         let op = LLVMConstInt(LLVMInt8Type(), op_value as u64, 0);
+        let rs1 = LLVMBuildIntCast(self.builder, rs1, LLVMInt8Type(), NONAME);
+        let rs2 = LLVMBuildIntCast(self.builder, rs2, LLVMInt8Type(), NONAME);
+        let rs3 = LLVMBuildIntCast(self.builder, rs3, LLVMInt8Type(), NONAME);
         let rd = self.section.emit_call_with_name(
             "banshee_fp8_op",
             [rs1, rs2, rs3, op, fpmode_dst],
@@ -4392,6 +4395,7 @@ impl<'a> InstructionTranslator<'a> {
                     fpmode_dst,
                 );
                 self.write_freg_f16(data.rd, value);
+                return Ok(());
             }
             riscv::OpcodeRdRs1::FcvtDH => {
                 let (fpmode_src, fpmode_dst) = self.read_fpmode();
@@ -10307,6 +10311,15 @@ impl<'a> InstructionTranslator<'a> {
             NONAME,
         );
 
+        let data0 = LLVMBuildIntCast(self.builder, data0, LLVMInt8Type(), NONAME);
+        let data1 = LLVMBuildIntCast(self.builder, data1, LLVMInt8Type(), NONAME);
+        let data2 = LLVMBuildIntCast(self.builder, data2, LLVMInt8Type(), NONAME);
+        let data3 = LLVMBuildIntCast(self.builder, data3, LLVMInt8Type(), NONAME);
+        let data4 = LLVMBuildIntCast(self.builder, data4, LLVMInt8Type(), NONAME);
+        let data5 = LLVMBuildIntCast(self.builder, data5, LLVMInt8Type(), NONAME);
+        let data6 = LLVMBuildIntCast(self.builder, data6, LLVMInt8Type(), NONAME);
+        let data7 = LLVMBuildIntCast(self.builder, data7, LLVMInt8Type(), NONAME);
+
         LLVMBuildStore(self.builder, data0, ptr_0);
         LLVMBuildStore(self.builder, data1, ptr_1);
         LLVMBuildStore(self.builder, data2, ptr_2);
@@ -10442,9 +10455,11 @@ impl<'a> InstructionTranslator<'a> {
     /// Emit the code to write a f8 value to a float register.
     unsafe fn write_freg_f8(&self, rd: u32, data: LLVMValueRef) {
         // Nan-box value
-        let nan_box = LLVMConstInt(LLVMInt64Type(), (-1i32 - 0xff) as u64, 0);
+        let data = LLVMBuildIntCast(self.builder, data, LLVMInt8Type(), NONAME);
+        let nan_box = LLVMConstInt(LLVMInt32Type(), (-1i32 - 0xff) as u64, 0);
         let value = LLVMBuildZExt(self.builder, data, LLVMInt32Type(), NONAME);
         let value = LLVMBuildOr(self.builder, nan_box, value, NONAME);
+        let value = LLVMBuildIntCast(self.builder, value, LLVMInt32Type(), NONAME);
 
         // Store value
         let ptr = self.reg_ptr(rd);