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Separate config registers from the LLC implementation #5
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@@ -13,3 +13,4 @@ sources*.txt | |
| pickle | ||
| doc/morty* | ||
| bender | ||
| morty* | ||
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| // Copyright 2018-2021 ETH Zurich and University of Bologna. | ||
| // Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| // SPDX-License-Identifier: SHL-0.51 | ||
| // | ||
| // Authors: | ||
| // Nicole Narr <narrn@ethz.ch> | ||
| // Christopher Reinwardt <creinwar@ethz.ch> | ||
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| { | ||
| name: "axi_llc", | ||
| clock_primary: "clk_i", | ||
| bus_interfaces: [ | ||
| { protocol: "reg_iface", direction: "device" } | ||
| ], | ||
| regwidth: 32, | ||
| registers: [ | ||
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| { name: "CFG_SPM_LOW", | ||
| desc: "SPM Configuration (lower 32 bit)", | ||
| swaccess: "rw", | ||
| hwaccess: "hrw", | ||
| fields: [ | ||
| {bits: "31:0", resval: 0, name: "low", desc: "lower 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "CFG_SPM_HIGH", | ||
| desc: "SPM Configuration (upper 32 bit)", | ||
| swaccess: "rw", | ||
| hwaccess: "hrw", | ||
| fields: [ | ||
| {bits: "31:0", name: "high", desc: "upper 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "CFG_FLUSH_LOW", | ||
| desc: "Flush Configuration (lower 32 bit)", | ||
| swaccess: "rw", | ||
| hwaccess: "hrw", | ||
| fields: [ | ||
| {bits: "31:0", name: "low", desc: "lower 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "CFG_FLUSH_HIGH", | ||
| desc: "Flush Configuration (upper 32 bit)", | ||
| swaccess: "rw", | ||
| hwaccess: "hrw", | ||
| fields: [ | ||
| {bits: "31:0", name: "high", desc: "upper 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "COMMIT_CFG", | ||
| desc: "Commit the configuration", | ||
| swaccess: "rw1s", | ||
| hwaccess: "hrw", | ||
| fields: [ | ||
| {bits: "0", name: "commit", desc: "commit configuration"} | ||
| ] | ||
| }, | ||
| {skipto: "0x18"} | ||
| { name: "FLUSHED_LOW", | ||
| desc: "Flushed Flag (lower 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hrw", | ||
| fields: [ | ||
| {bits: "31:0", name: "low", desc: "lower 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "FLUSHED_HIGH", | ||
| desc: "Flushed Flag (upper 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hrw", | ||
| fields: [ | ||
| {bits: "31:0", name: "high", desc: "upper 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "BIST_OUT_LOW", | ||
| desc: "Tag Storage BIST Result (lower 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hwo", | ||
| fields: [ | ||
| {bits: "31:0", name: "low", desc: "lower 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "BIST_OUT_HIGH", | ||
| desc: "Tag Storage BIST Result (upper 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hwo", | ||
| fields: [ | ||
| {bits: "31:0", name: "high", desc: "upper 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "SET_ASSO_LOW", | ||
| desc: "Instantiated Set-Associativity (lower 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hwo", | ||
| fields: [ | ||
| {bits: "31:0", name: "low", desc: "lower 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "SET_ASSO_HIGH", | ||
| desc: "Instantiated Set-Associativity (upper 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hwo", | ||
| fields: [ | ||
| {bits: "31:0", name: "high", desc: "upper 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "NUM_LINES_LOW", | ||
| desc: "Instantiated Number of Cache-Lines (lower 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hwo", | ||
| fields: [ | ||
| {bits: "31:0", name: "low", desc: "lower 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "NUM_LINES_HIGH", | ||
| desc: "Instantiated Number of Cache-Lines (upper 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hwo", | ||
| fields: [ | ||
| {bits: "31:0", name: "high", desc: "upper 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "NUM_BLOCKS_LOW", | ||
| desc: "Instantiated Number of Blocks (lower 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hwo", | ||
| fields: [ | ||
| {bits: "31:0", name: "low", desc: "lower 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "NUM_BLOCKS_HIGH", | ||
| desc: "Instantiated Number of Blocks (upper 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hwo", | ||
| fields: [ | ||
| {bits: "31:0", name: "high", desc: "upper 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "VERSION_LOW", | ||
| desc: "AXI LLC Version (lower 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hwo", | ||
| fields: [ | ||
| {bits: "31:0", name: "low", desc: "lower 32 bit"} | ||
| ] | ||
| }, | ||
| { name: "VERSION_HIGH", | ||
| desc: "AXI LLC Version (upper 32 bit)", | ||
| swaccess: "ro", | ||
| hwaccess: "hwo", | ||
| fields: [ | ||
| {bits: "31:0", name: "high", desc: "upper 32 bit"} | ||
| ] | ||
| } | ||
| ] | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,44 @@ | ||
| // Copyright 2022 ETH Zurich and University of Bologna. | ||
| // Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| // SPDX-License-Identifier: SHL-0.51 | ||
| // | ||
| // Authors: | ||
| // - Nicole Narr <narrn@ethz.ch> | ||
| // - Christopher Reinwardt <creinwar@ethz.ch> | ||
| // Date: 17.11.2022 | ||
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| // Macros to connect AXI_LLC config registers | ||
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| `ifndef AXI_LLC_ASSIGN_SVH_ | ||
| `define AXI_LLC_ASSIGN_SVH_ | ||
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| // Assign the regtool RegBus 32-bit HW2REG _low, _high and enable signals from the | ||
| // 64-bit d_struct member with the same name | ||
| `define AXI_LLC_ASSIGN_REGBUS_FROM_REGS_D_MEMBER(regbus, d_struct, member) \ | ||
| assign regbus.member``_low.d = d_struct.member; \ | ||
| assign regbus.member``_low.de = d_struct.member``_en; \ | ||
| assign regbus.member``_high.d = d_struct.member >> 32; \ | ||
| assign regbus.member``_high.de = d_struct.member``_en; | ||
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| // Assign the regtool RegBus HW2REG struct from a d_struct | ||
| `define AXI_LLC_ASSIGN_REGBUS_FROM_REGS_D(regbus, d_struct) \ | ||
| `AXI_LLC_ASSIGN_REGBUS_FROM_REGS_D_MEMBER(regbus, d_struct, cfg_spm) \ | ||
| `AXI_LLC_ASSIGN_REGBUS_FROM_REGS_D_MEMBER(regbus, d_struct, cfg_flush) \ | ||
| assign regbus.commit_cfg.d = d_struct.commit_cfg; \ | ||
| assign regbus.commit_cfg.de = d_struct.commit_cfg_en; \ | ||
| `AXI_LLC_ASSIGN_REGBUS_FROM_REGS_D_MEMBER(regbus, d_struct, flushed) \ | ||
| `AXI_LLC_ASSIGN_REGBUS_FROM_REGS_D_MEMBER(regbus, d_struct, bist_out) \ | ||
| `AXI_LLC_ASSIGN_REGBUS_FROM_REGS_D_MEMBER(regbus, d_struct, set_asso) \ | ||
| `AXI_LLC_ASSIGN_REGBUS_FROM_REGS_D_MEMBER(regbus, d_struct, num_lines) \ | ||
| `AXI_LLC_ASSIGN_REGBUS_FROM_REGS_D_MEMBER(regbus, d_struct, num_blocks) \ | ||
| `AXI_LLC_ASSIGN_REGBUS_FROM_REGS_D_MEMBER(regbus, d_struct, version) | ||
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| // Assign the 64-bit q_struct values from the corresponding 32-bit _low and _high | ||
| // REG2HW signals | ||
| `define AXI_LLC_ASSIGN_REGS_Q_FROM_REGBUS(q_struct, regbus) \ | ||
| assign q_struct.cfg_spm = {regbus.cfg_spm_high.q, regbus.cfg_spm_low.q}; \ | ||
| assign q_struct.cfg_flush = {regbus.cfg_flush_high.q, regbus.cfg_flush_low.q}; \ | ||
| assign q_struct.commit_cfg = regbus.commit_cfg.q; \ | ||
| assign q_struct.flushed = {regbus.flushed_high.q, regbus.flushed_low.q}; | ||
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| `endif |
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