Processor-Centric Contention-aware Slowdown Model

Processor-centric contention-aware slowdown model is a slowdown model for shared memory SoCs. This page includes the code that is used to construct this model. The code is primarily tested on two devices: (1) NVIDIA Jetson Xavier and (2) Qualcomm Snapdragon 855.

Introduction & Usage

The model construction has two steps. First step is to run all different bandwidth kernels on the target PU under all different external bandwidth demands. The external bandwidth demand is generated by running these kernels on other PUs. The result is recorded as a two-dimensional matrix that the $element[i][j]$ in this matrix means the achieved relative speeds of i-th smallest kernel running on the target PU over the j-th smallest external BW demands.

The second step is to analyse the above matrix to determine model parameters by running the model construction code.

Pseudo code

Folder Structure

• corun: The code to generate different bandwidth on processors.
• model construction: The code and sample input to construct the model.

Credits

The kernel code is inspired by CS Roofline toolkit