Skip to content

Commit

Permalink
Backport RTL8125B support
Browse files Browse the repository at this point in the history
  • Loading branch information
@jackpot51
jackpot51 committed Aug 13, 2020
1 parent 47aab50 commit d2542ef
Showing 1 changed file with 142 additions and 20 deletions.
162 changes: 142 additions & 20 deletions drivers/net/ethernet/realtek/r8169_main.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,7 @@
#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
#define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"

#define R8169_MSG_DEFAULT \
(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
Expand Down Expand Up @@ -137,6 +138,7 @@ enum mac_version {
RTL_GIGA_MAC_VER_51,
RTL_GIGA_MAC_VER_60,
RTL_GIGA_MAC_VER_61,
RTL_GIGA_MAC_VER_63,
RTL_GIGA_MAC_NONE
};

Expand Down Expand Up @@ -204,6 +206,8 @@ static const struct {
[RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
[RTL_GIGA_MAC_VER_60] = {"RTL8125" },
[RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3},
/* reserve 62 for CFG_METHOD_4 in the vendor driver */
[RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
};

static const struct pci_device_id rtl8169_pci_tbl[] = {
Expand Down Expand Up @@ -395,6 +399,7 @@ enum rtl8125_registers {
IntrStatus_8125 = 0x3c,
TxPoll_8125 = 0x90,
MAC0_BKP = 0x19e0,
EEE_TXIDLE_TIMER_8125 = 0x6048,
};

#define RX_VLAN_INNER_8125 BIT(22)
Expand Down Expand Up @@ -716,6 +721,7 @@ MODULE_FIRMWARE(FIRMWARE_8168H_2);
MODULE_FIRMWARE(FIRMWARE_8107E_1);
MODULE_FIRMWARE(FIRMWARE_8107E_2);
MODULE_FIRMWARE(FIRMWARE_8125A_3);
MODULE_FIRMWARE(FIRMWARE_8125B_2);

static inline struct device *tp_to_dev(struct rtl8169_private *tp)
{
Expand Down Expand Up @@ -1056,7 +1062,7 @@ static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
case RTL_GIGA_MAC_VER_31:
r8168dp_2_mdio_write(tp, location, val);
break;
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
r8168g_mdio_write(tp, location, val);
break;
default:
Expand All @@ -1073,7 +1079,7 @@ static int rtl_readphy(struct rtl8169_private *tp, int location)
case RTL_GIGA_MAC_VER_28:
case RTL_GIGA_MAC_VER_31:
return r8168dp_2_mdio_read(tp, location);
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
return r8168g_mdio_read(tp, location);
default:
return r8169_mdio_read(tp, location);
Expand Down Expand Up @@ -1504,7 +1510,7 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
break;
case RTL_GIGA_MAC_VER_34:
case RTL_GIGA_MAC_VER_37:
case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51:
case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
if (wolopts)
options |= PME_SIGNAL;
Expand Down Expand Up @@ -2140,7 +2146,10 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp)
u16 val;
u16 mac_version;
} mac_info[] = {
/* 8125 family. */
/* 8125B family. */
{ 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },

/* 8125A family. */
{ 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
{ 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },

Expand Down Expand Up @@ -2297,6 +2306,17 @@ static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
}

static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
{
RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
}

static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
{
rtl8125_set_eee_txidle_timer(tp);
r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
}

static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
{
struct phy_device *phydev = tp->phydev;
Expand Down Expand Up @@ -2337,6 +2357,16 @@ static void rtl8125_config_eee_phy(struct rtl8169_private *tp)
phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
}

static void rtl8125b_config_eee_phy(struct rtl8169_private *tp)
{
struct phy_device *phydev = tp->phydev;

phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
phy_modify_paged(phydev, 0xa42, 0x14, 0x0080, 0x0000);
phy_modify_paged(phydev, 0xa4a, 0x11, 0x0200, 0x0000);
}

static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
{
static const struct phy_reg phy_reg_init[] = {
Expand Down Expand Up @@ -3785,6 +3815,59 @@ static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp)
rtl_enable_eee(tp);
}

static void r8168g_phy_param(struct phy_device *phydev, u16 parm,
u16 mask, u16 val)
{
int oldpage = phy_select_page(phydev, 0x0a43);

__phy_write(phydev, 0x13, parm);
__phy_modify(phydev, 0x14, mask, val);

phy_restore_page(phydev, oldpage, 0);
}

static void rtl8125b_hw_phy_config(struct rtl8169_private *tp)
{
struct phy_device *phydev = tp->phydev;

rtl_apply_firmware(tp);

phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
phy_modify_paged(phydev, 0xac4, 0x13, 0x00f0, 0x0090);
phy_modify_paged(phydev, 0xad3, 0x10, 0x0003, 0x0001);

phy_write(phydev, 0x1f, 0x0b87);
phy_write(phydev, 0x16, 0x80f5);
phy_write(phydev, 0x17, 0x760e);
phy_write(phydev, 0x16, 0x8107);
phy_write(phydev, 0x17, 0x360e);
phy_write(phydev, 0x16, 0x8551);
phy_modify(phydev, 0x17, 0xff00, 0x0800);
phy_write(phydev, 0x1f, 0x0000);

phy_modify_paged(phydev, 0xbf0, 0x10, 0xe000, 0xa000);
phy_modify_paged(phydev, 0xbf4, 0x13, 0x0f00, 0x0300);

r8168g_phy_param(phydev, 0x8044, 0xffff, 0x2417);
r8168g_phy_param(phydev, 0x804a, 0xffff, 0x2417);
r8168g_phy_param(phydev, 0x8050, 0xffff, 0x2417);
r8168g_phy_param(phydev, 0x8056, 0xffff, 0x2417);
r8168g_phy_param(phydev, 0x805c, 0xffff, 0x2417);
r8168g_phy_param(phydev, 0x8062, 0xffff, 0x2417);
r8168g_phy_param(phydev, 0x8068, 0xffff, 0x2417);
r8168g_phy_param(phydev, 0x806e, 0xffff, 0x2417);
r8168g_phy_param(phydev, 0x8074, 0xffff, 0x2417);
r8168g_phy_param(phydev, 0x807a, 0xffff, 0x2417);

phy_modify_paged(phydev, 0xa4c, 0x15, 0x0000, 0x0040);
phy_modify_paged(phydev, 0xbf8, 0x12, 0xe000, 0xa000);

// rtl8125_legacy_force_mode in upstream
phy_modify_paged(phydev, 0xa5b, 0x12, BIT(15), 0);

rtl8125b_config_eee_phy(tp);
}

static void rtl_hw_phy_config(struct net_device *dev)
{
static const rtl_generic_fct phy_configs[] = {
Expand Down Expand Up @@ -3842,6 +3925,7 @@ static void rtl_hw_phy_config(struct net_device *dev)
[RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
[RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config,
[RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config,
[RTL_GIGA_MAC_VER_61] = rtl8125b_hw_phy_config,
};
struct rtl8169_private *tp = netdev_priv(dev);

Expand Down Expand Up @@ -3933,7 +4017,7 @@ static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
case RTL_GIGA_MAC_VER_32:
case RTL_GIGA_MAC_VER_33:
case RTL_GIGA_MAC_VER_34:
case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61:
case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_63:
RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
break;
Expand Down Expand Up @@ -3967,10 +4051,7 @@ static void rtl_pll_power_down(struct rtl8169_private *tp)
case RTL_GIGA_MAC_VER_46:
case RTL_GIGA_MAC_VER_47:
case RTL_GIGA_MAC_VER_48:
case RTL_GIGA_MAC_VER_50:
case RTL_GIGA_MAC_VER_51:
case RTL_GIGA_MAC_VER_60:
case RTL_GIGA_MAC_VER_61:
case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
break;
case RTL_GIGA_MAC_VER_40:
Expand Down Expand Up @@ -3998,10 +4079,7 @@ static void rtl_pll_power_up(struct rtl8169_private *tp)
case RTL_GIGA_MAC_VER_46:
case RTL_GIGA_MAC_VER_47:
case RTL_GIGA_MAC_VER_48:
case RTL_GIGA_MAC_VER_50:
case RTL_GIGA_MAC_VER_51:
case RTL_GIGA_MAC_VER_60:
case RTL_GIGA_MAC_VER_61:
case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
break;
case RTL_GIGA_MAC_VER_40:
Expand Down Expand Up @@ -4034,7 +4112,7 @@ static void rtl_init_rxcfg(struct rtl8169_private *tp)
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
break;
case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
RX_DMA_BURST);
break;
Expand Down Expand Up @@ -5271,18 +5349,27 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
/* disable new tx descriptor format */
r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);

r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
if (tp->mac_version == RTL_GIGA_MAC_VER_63)
r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
else
r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);

if (tp->mac_version == RTL_GIGA_MAC_VER_63)
r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
else
r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);

r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);

r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
udelay(1);
Expand All @@ -5293,7 +5380,10 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp)

rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);

rtl8125_config_eee_mac(tp);
if (tp->mac_version == RTL_GIGA_MAC_VER_63)
rtl8125b_config_eee_mac(tp);
else
rtl8125_config_eee_mac(tp);

RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
udelay(10);
Expand Down Expand Up @@ -5336,6 +5426,7 @@ static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
rtl_ephy_init(tp, e_info_8125_1);

rtl_hw_start_8125_common(tp);
rtl_hw_aspm_clkreq_enable(tp, true);
}

static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
Expand Down Expand Up @@ -5363,6 +5454,27 @@ static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
rtl_ephy_init(tp, e_info_8125_2);

rtl_hw_start_8125_common(tp);
rtl_hw_aspm_clkreq_enable(tp, true);
}

static void rtl_hw_start_8125b(struct rtl8169_private *tp)
{
static const struct ephy_info e_info_8125b[] = {
{ 0x0b, 0xffff, 0xa908 },
{ 0x1e, 0xffff, 0x20eb },
{ 0x4b, 0xffff, 0xa908 },
{ 0x5e, 0xffff, 0x20eb },
{ 0x22, 0x0030, 0x0020 },
{ 0x62, 0x0030, 0x0020 },
};

rtl_set_def_aspm_entry_latency(tp);
rtl_hw_aspm_clkreq_enable(tp, false);

rtl_ephy_init(tp, e_info_8125b);
rtl_hw_start_8125_common(tp);

rtl_hw_aspm_clkreq_enable(tp, true);
}

static void rtl_hw_config(struct rtl8169_private *tp)
Expand Down Expand Up @@ -5415,6 +5527,7 @@ static void rtl_hw_config(struct rtl8169_private *tp)
[RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
[RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
[RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
[RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
};

if (hw_configs[tp->mac_version])
Expand Down Expand Up @@ -5514,6 +5627,15 @@ static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
dev->mtu = new_mtu;
netdev_update_features(dev);

switch (tp->mac_version) {
case RTL_GIGA_MAC_VER_61:
case RTL_GIGA_MAC_VER_63:
rtl8125_set_eee_txidle_timer(tp);
break;
default:
break;
}

return 0;
}

Expand Down Expand Up @@ -6980,7 +7102,7 @@ static void rtl_hw_initialize(struct rtl8169_private *tp)
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
rtl_hw_init_8168g(tp);
break;
case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
rtl_hw_init_8125(tp);
break;
default:
Expand Down

0 comments on commit d2542ef

Please sign in to comment.