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feat: Add new STM32H5 family to hal-st (#365)
* Add HAL and CMSIS Drivers Add HAL and CMSIS drivers from the STM32CubeH5 MCU Firmware Package version v1.3.0. Add HAL driver v1.3.0 from https://github.com/STMicroelectronics/stm32h5xx_hal_driver Adds CMSIS core drivers v1.3.0 from https://github.com/STMicroelectronics/STM32CubeH5 Adds CMSIS device drivers v1.3.0 from https://github.com/STMicroelectronics/cmsis_device_h5 * Adjust startup procedure to call into Default_Handler_Forwarded * Bringup STM32H5xx series * Add differentiation for ADC channel types ADC channel types might be P or N which is used for the ADC's differencial function. Only select the P type channels if present.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,52 @@ | ||
| #include DEVICE_HEADER | ||
| #include "hal_st/stm32fxxx/DefaultClockDiscoveryH573I.hpp" | ||
|
|
||
| /* The system Clock is configured as follows: | ||
| * System Clock source = PLL (HSE) | ||
| * SYSCLK(Hz) = 250000000 | ||
| * HCLK(Hz) = 250000000 | ||
| * AHB Prescaler = 1 | ||
| * APB1 Prescaler = 1 | ||
| * APB2 Prescaler = 1 | ||
| * APB3 Prescaler = 1 | ||
| * HSE Frequency(Hz) = 25MHz | ||
| * VDD(V) = 3.3 | ||
| * Main regulator output voltage = Scale0 mode | ||
| */ | ||
| void ConfigureDefaultClockDiscoveryH573I() | ||
| { | ||
| RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; | ||
| RCC_OscInitTypeDef RCC_OscInitStruct = {}; | ||
|
|
||
| // Configure the main internal regulator output voltage | ||
| __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); | ||
|
|
||
| while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) | ||
| { | ||
| } | ||
|
|
||
| // Enable HSE Oscillator and activate PLL with HSE as source | ||
| RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; | ||
| RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; | ||
| RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; | ||
| RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; | ||
| RCC_OscInitStruct.PLL.PLLM = 2; // Divides the 25MHz HSE to 12.5MHz | ||
| RCC_OscInitStruct.PLL.PLLN = 40; // Multiplies the 12.5MHz to 500MHz | ||
| RCC_OscInitStruct.PLL.PLLP = 2; // Divides the 500MHz to 250MHz for SYSCLK | ||
| RCC_OscInitStruct.PLL.PLLQ = 2; | ||
| RCC_OscInitStruct.PLL.PLLR = 2; | ||
| RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_3; | ||
| RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; | ||
| RCC_OscInitStruct.PLL.PLLFRACN = 0; | ||
| HAL_RCC_OscConfig(&RCC_OscInitStruct); | ||
|
|
||
| // Select PLL as system clock source and configure the HCLK, PCLK1, PCLK2 and PCLK3 | ||
| // clocks dividers | ||
| RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; | ||
| RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; | ||
| RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; | ||
| RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; | ||
| RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; | ||
| RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; | ||
| HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,6 @@ | ||
| #ifndef HAL_ST_DEFAULT_CLOCK_HPP | ||
| #define HAL_ST_DEFAULT_CLOCK_HPP | ||
|
|
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| void ConfigureDefaultClockDiscoveryH573I(); | ||
|
|
||
| #endif |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,52 @@ | ||
| #include DEVICE_HEADER | ||
| #include "hal_st/stm32fxxx/DefaultClockNucleoH563ZI.hpp" | ||
|
|
||
| /* The system Clock is configured as follows: | ||
| * System Clock source = PLL (HSE) | ||
| * SYSCLK(Hz) = 250000000 | ||
| * HCLK(Hz) = 250000000 | ||
| * AHB Prescaler = 1 | ||
| * APB1 Prescaler = 1 | ||
| * APB2 Prescaler = 1 | ||
| * APB3 Prescaler = 1 | ||
| * HSE Frequency(Hz) = 8MHz | ||
| * VDD(V) = 3.3 | ||
| * Main regulator output voltage = Scale0 mode | ||
| */ | ||
| void ConfigureDefaultClockNucleoH563ZI() | ||
| { | ||
| RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; | ||
| RCC_OscInitTypeDef RCC_OscInitStruct = {}; | ||
|
|
||
| // Configure the main internal regulator output voltage | ||
| __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); | ||
|
|
||
| while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) | ||
| { | ||
| } | ||
|
|
||
| // Enable HSE Oscillator and activate PLL with HSE as source | ||
| RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; | ||
| RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; | ||
| RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; | ||
| RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; | ||
| RCC_OscInitStruct.PLL.PLLM = 4; // Divides the 8MHz HSI to 2MHz | ||
| RCC_OscInitStruct.PLL.PLLN = 250; // Multiplies the 2MHz to 500MHz | ||
| RCC_OscInitStruct.PLL.PLLP = 2; // Divides the 500MHz to 250MHz for SYSCLK | ||
| RCC_OscInitStruct.PLL.PLLQ = 2; | ||
| RCC_OscInitStruct.PLL.PLLR = 2; | ||
| RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; | ||
| RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; | ||
| RCC_OscInitStruct.PLL.PLLFRACN = 0; | ||
| HAL_RCC_OscConfig(&RCC_OscInitStruct); | ||
|
|
||
| // Select PLL as system clock source and configure the HCLK, PCLK1, PCLK2 and PCLK3 | ||
| // clocks dividers | ||
| RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; | ||
| RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; | ||
| RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; | ||
| RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; | ||
| RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; | ||
| RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; | ||
| HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,6 @@ | ||
| #ifndef HAL_ST_DEFAULT_CLOCK_HPP | ||
| #define HAL_ST_DEFAULT_CLOCK_HPP | ||
|
|
||
| void ConfigureDefaultClockNucleoH563ZI(); | ||
|
|
||
| #endif |
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