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  1. scr1 scr1 Public

    Forked from syntacore/scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    SystemVerilog 1

  2. core-v-verif core-v-verif Public

    Forked from openhwgroup/core-v-verif

    Functional verification project for the CORE-V family of RISC-V cores.

    Assembly

  3. cv32e40p cv32e40p Public

    Forked from openhwgroup/cv32e40p

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog

  4. core-v-docs core-v-docs Public

    Forked from openhwgroup/programs

    Documentation for the OpenHW Group's set of CORE-V RISC-V cores

    HTML 1

  5. cvfpu cvfpu Public

    Forked from openhwgroup/cvfpu

    Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

    SystemVerilog

  6. core-v-sw core-v-sw Public

    Forked from openhwgroup/core-v-sw

    Main Repo for the OpenHW Group Software Task Group