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    298 repositories

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •22•71•5•3•Updated Feb 25, 2025Feb 25, 2025

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •29•120•7•7•Updated Feb 25, 2025Feb 25, 2025

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •36•40•7•4•Updated Feb 25, 2025Feb 25, 2025

    • regression_tests

      Public
      C
      •17•8•3•1•Updated Feb 25, 2025Feb 25, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •19•91•1•2•Updated Feb 25, 2025Feb 25, 2025

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •11•12•4•3•Updated Feb 25, 2025Feb 25, 2025

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •68•1•0•2•Updated Feb 25, 2025Feb 25, 2025

    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      •
      Other
      •542•0•0•2•Updated Feb 25, 2025Feb 25, 2025

    • u-boot

      Public
      Unofficial development fork of U-Boot
      C
      •12•0•0•1•Updated Feb 25, 2025Feb 25, 2025

    • pulp-nnx

      Public
      C
      •
      Apache License 2.0
      •0•4•0•0•Updated Feb 25, 2025Feb 25, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •53•227•9•17•Updated Feb 25, 2025Feb 25, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •11•26•9•3•Updated Feb 25, 2025Feb 25, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •8•53•1•0•Updated Feb 24, 2025Feb 24, 2025

    • hwpe-stream

      Public
      IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •19•19•2•3•Updated Feb 24, 2025Feb 24, 2025

    • neureka

      Public
      2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
      SystemVerilog
      •
      Other
      •3•19•4•1•Updated Feb 24, 2025Feb 24, 2025

    • redundancy_cells

      Public
      SystemVerilog IPs and Modules for architectural redundancy designs.
      SystemVerilog
      •
      Other
      •7•10•0•6•Updated Feb 24, 2025Feb 24, 2025

    • scm

      Public
      SystemVerilog
      •
      Other
      •5•3•0•1•Updated Feb 24, 2025Feb 24, 2025

    • cv32e40p

      Public
      CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
      SystemVerilog
      •
      Other
      •436•19•0•0•Updated Feb 24, 2025Feb 24, 2025

    • cluster_peripherals

      Public
      SystemVerilog
      •
      Other
      •4•1•0•0•Updated Feb 24, 2025Feb 24, 2025

    • cluster_icache

      Public
      An instruction cache for processor clusters, originally developed for the snitch cluster.
      SystemVerilog
      •
      Other
      •2•2•0•5•Updated Feb 24, 2025Feb 24, 2025

    • hier-icache

      Public
      SystemVerilog
      •
      Other
      •10•11•0•1•Updated Feb 24, 2025Feb 24, 2025

    • event_unit_flex

      Public
      SystemVerilog
      •
      Other
      •4•2•0•2•Updated Feb 24, 2025Feb 24, 2025

    • mchan

      Public
      SystemVerilog
      •
      Other
      •5•1•1•0•Updated Feb 24, 2025Feb 24, 2025

    • axi2per

      Public
      AXI to Peripheral Interconnect
      asicfpgaaxisystemverilog-hdl
      SystemVerilog
      •
      Other
      •1•6•0•0•Updated Feb 24, 2025Feb 24, 2025

    • cluster_interconnect

      Public
      SystemVerilog
      •
      Other
      •15•12•1•2•Updated Feb 24, 2025Feb 24, 2025

    • per2axi

      Public
      Peripheral Bus to AXI adapter
      SystemVerilog
      •
      Other
      •2•0•0•0•Updated Feb 24, 2025Feb 24, 2025

    • axi2mem

      Public
      SystemVerilog
      •
      Other
      •6•5•1•0•Updated Feb 24, 2025Feb 24, 2025

    • hwpe-ctrl

      Public
      IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •17•6•1•4•Updated Feb 24, 2025Feb 24, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •724•17•0•6•Updated Feb 22, 2025Feb 22, 2025

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •138•400•68•6•Updated Feb 22, 2025Feb 22, 2025