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    295 repositories

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •50•212•9•19•Updated Jan 7, 2025Jan 7, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •18•82•1•3•Updated Jan 7, 2025Jan 7, 2025

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •132•389•64•8•Updated Jan 7, 2025Jan 7, 2025

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •29•113•7•5•Updated Jan 7, 2025Jan 7, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •272•1.2k•44•9•Updated Jan 7, 2025Jan 7, 2025

    • common_verification

      Public
      SystemVerilog modules and classes commonly used for verification
      SystemVerilog
      •
      Other
      •14•44•0•2•Updated Jan 7, 2025Jan 7, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •46•279•3•4•Updated Jan 7, 2025Jan 7, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •6•43•0•0•Updated Jan 7, 2025Jan 7, 2025

    • svase

      Public
      C++
      •
      Apache License 2.0
      •2•31•1•0•Updated Jan 7, 2025Jan 7, 2025

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •14•5•0•6•Updated Jan 7, 2025Jan 7, 2025

    • ManyRVData

      Public
      0•0•0•0•Updated Jan 7, 2025Jan 7, 2025

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •15•21•3•10•Updated Jan 6, 2025Jan 6, 2025

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •14•74•16•6•Updated Jan 5, 2025Jan 5, 2025

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •117•12•0•4•Updated Jan 3, 2025Jan 3, 2025

    • memory_island

      Public
      An interleaved high-throughput low-contention L2 scratchpad memory.
      SystemVerilog
      •
      Other
      •2•2•4•3•Updated Jan 3, 2025Jan 3, 2025

    • chimera

      Public
      Python
      •
      Other
      •2•13•9•1•Updated Jan 3, 2025Jan 3, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •58•57•15•7•Updated Dec 30, 2024Dec 30, 2024

    • pulp-nnx

      Public
      C
      •
      Apache License 2.0
      •0•4•0•0•Updated Dec 30, 2024Dec 30, 2024

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •706•17•1•8•Updated Dec 20, 2024Dec 20, 2024

    • pulp-detector

      Public
      C
      •2•12•1•0•Updated Dec 20, 2024Dec 20, 2024

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •25•153•10•4•Updated Dec 20, 2024Dec 20, 2024

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •21•63•4•4•Updated Dec 19, 2024Dec 19, 2024

    • regression_tests

      Public
      C
      •16•7•3•1•Updated Dec 19, 2024Dec 19, 2024

    • chimera-sdk

      Public
      Python
      •
      Apache License 2.0
      •3•3•6•5•Updated Dec 19, 2024Dec 19, 2024

    • quantlib

      Public
      A library to train and deploy quantised Deep Neural Networks
      Python
      •
      Apache License 2.0
      •8•21•2•1•Updated Dec 18, 2024Dec 18, 2024

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •40•273•25•5•Updated Dec 18, 2024Dec 18, 2024

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •9•19•4•3•Updated Dec 12, 2024Dec 12, 2024

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •16•28•4•3•Updated Dec 12, 2024Dec 12, 2024

    • occamy

      Public
      A high-efficiency system-on-chip for floating-point compute workloads.
      Python
      •
      Apache License 2.0
      •13•17•7•1•Updated Dec 10, 2024Dec 10, 2024

    • pulp-ethernet

      Public
      SystemVerilog
      •
      Other
      •1•9•0•2•Updated Dec 10, 2024Dec 10, 2024