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@iic-jku Institute for Integrated Circuits, Johannes Kepler University Linz

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    44 repositories

    • padring

      Public
      A padring generator for ASICs
      C++
      •
      ISC License
      •9•0•0•0•Updated Dec 27, 2024Dec 27, 2024

    • IIC-OSIC-TOOLS

      Public
      IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
      circuitsicdigital-designmicroelectronicsanalog-designmixed-signal-chips
      Python
      •
      Apache License 2.0
      •79•373•9•2•Updated Dec 26, 2024Dec 26, 2024

    • analog-circuit-design

      Public
      Course material for a basic-level circuit design course using Xschem and ngspice
      Jupyter Notebook
      •
      Apache License 2.0
      •10•50•0•0•Updated Dec 17, 2024Dec 17, 2024

    • BTLE

      Public
      Bluetooth Low Energy (BLE) packet sniffer and transmitter for both standard and non standard (raw bit) based on Software Defined Radio (SDR).
      Jupyter Notebook
      •
      Apache License 2.0
      •137•1•0•0•Updated Dec 2, 2024Dec 2, 2024

    • osic-multitool

      Public
      JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
      magicnetgenngspicelvsopenlanesky130xschem
      Shell
      •
      Apache License 2.0
      •14•56•1•0•Updated Nov 15, 2024Nov 15, 2024

    • Circuit-Designers-Etiquette

      Public
      A set of rules and recommendations for analog and digital circuit designers.
      Apache License 2.0
      •0•26•3•0•Updated Nov 4, 2024Nov 4, 2024

    • ttihp-0p2-hpretl-minilogix

      Public
      A simple 8b input, 8b output freely programmable logic block with optional selectable feedback.
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Nov 2, 2024Nov 2, 2024

    • ttihp0p2-um-hpretl-spi

      Public
      Simple SPI-based register file (for the testing the flow)
      Verilog
      •
      Apache License 2.0
      •0•1•0•0•Updated Oct 31, 2024Oct 31, 2024

    • openlane2

      Public
      The next generation of OpenLane, rewritten from scratch with a modular architecture
      Python
      •
      Apache License 2.0
      •41•0•0•1•Updated Sep 3, 2024Sep 3, 2024

    • mpw8-submission

      Public
      MPW-8 tapeout submission containing mixed-signal circuit blocks in SKY130
      Verilog
      •
      Apache License 2.0
      •0•4•0•1•Updated Sep 3, 2024Sep 3, 2024

    • Vlsir

      Public
      Interchange formats for chip design.
      TypeScript
      •
      BSD 3-Clause "New" or "Revised" License
      •11•0•0•1•Updated Aug 11, 2024Aug 11, 2024

    • SKY130_SAR-ADC1

      Public
      Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
      adcmixed-signalsky130icdesign
      Verilog
      •
      Apache License 2.0
      •8•38•0•0•Updated Jul 30, 2024Jul 30, 2024

    • IIC-RALF

      Public
      Reinforcement learning assisted analog layout design flow.
      Python
      •
      Apache License 2.0
      •7•11•0•0•Updated Jul 29, 2024Jul 29, 2024

    • ioplace_parser

      Public
      Antlr4-based parser for the input files to OpenLane custom IO placers.
      Python
      •1•0•0•1•Updated Jul 5, 2024Jul 5, 2024

    • tt05-analog-test

      Public
      Analog test macro (500kHz ring oscillator, 3-bit DAC) for TinyTapeout 05.
      Tcl
      •
      Apache License 2.0
      •2•4•1•0•Updated Jun 14, 2024Jun 14, 2024

    • jku-sfl-test-cells

      Public
      Flicker noise test cells for the IHP Open-Source PDK (SG13G2) for the MPW Tape-out May 2024.
      Apache License 2.0
      •0•0•0•0•Updated Jun 3, 2024Jun 3, 2024

    • kvosid_336004_ss24

      Public
      Course material for 336.004 (Prof. Pretl) in SS24 at JKU
      Python
      •1•0•0•0•Updated May 28, 2024May 28, 2024

    • SKY130_PLL1

      Public
      Implementation of a Sub-Sampling PLL targeting SerDes Applications in SKYWATER PDK 130nm process
      Verilog
      •2•5•0•0•Updated Apr 23, 2024Apr 23, 2024

    • jku-tt06-tdc-v2

      Public
      TDC based on simple inverter ring
      Verilog
      •
      Apache License 2.0
      •3•1•0•1•Updated Mar 30, 2024Mar 30, 2024

    • jku-tt06-tdc-v1

      Public
      TDC based on simple inverter chain
      Verilog
      •
      Apache License 2.0
      •3•4•0•0•Updated Mar 17, 2024Mar 17, 2024

    • jku-tt06-tempsens-ng

      Public
      Temperature sensor from standard cells
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Mar 10, 2024Mar 10, 2024

    • eda_docker

      Public
      A Docker Container based one CentOS 7 to run commercial EDA applications, that require a legacy OS environment.
      Shell
      •
      Apache License 2.0
      •0•2•0•0•Updated Feb 14, 2024Feb 14, 2024

    • skill-collection

      Public
      Helpful Cadence Skill Scrips
      Apache License 2.0
      •1•1•0•0•Updated Feb 5, 2024Feb 5, 2024

    • tt03-tempsensor

      Public
      Synthesizable temperature sensor for Tiny Tapeout 03, developed by IIC@JKU.
      Red
      •
      Apache License 2.0
      •205•20•0•0•Updated Jan 1, 2024Jan 1, 2024

    • sky130_adc_202311

      Public
      PLSQL
      •
      Apache License 2.0
      •89•6•0•0•Updated Nov 20, 2023Nov 20, 2023

    • OpenVAF

      Public
      An innovative Verilog-A compiler
      Rust
      •
      GNU General Public License v3.0
      •26•1•0•0•Updated Nov 1, 2023Nov 1, 2023

    • SKY130-RTL-with-Custom-Standardcell-to-GDSII

      Public
      Documentation for RTL-with-customcells to GDSII
      Verilog
      •
      Apache License 2.0
      •1•5•0•0•Updated Oct 25, 2023Oct 25, 2023

    • IHP-Open-PDK

      Public
      130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
      Python
      •
      Apache License 2.0
      •67•1•0•0•Updated Oct 24, 2023Oct 24, 2023

    • sky130_power_gate

      Public
      PMOS power gate for TinyTapeout
      Shell
      •
      Apache License 2.0
      •2•1•0•0•Updated Oct 20, 2023Oct 20, 2023

    • SKY130_CT-DSM

      Public
      A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the front-end Gm-cell and a mixed-signal simulation w/ Ngspice.
      Jupyter Notebook
      •
      Apache License 2.0
      •2•1•0•0•Updated Oct 1, 2023Oct 1, 2023