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    29 repositories

    • .github

      Public
      0•0•0•0•Updated Jan 15, 2024Jan 15, 2024

    • fpga-drive-aximm-pcie

      Public
      Example designs for FPGA Drive FMC
      Tcl
      •
      MIT License
      •99•0•0•0•Updated Nov 8, 2023Nov 8, 2023

    • FPGA-Adaptive-Beamforming-and-Radar-Examples

      Public
      This repository contains FPGA/HDL demonstrations several beamforming and radar designs. Simulink models and MATLAB reference code are provided to showcase high-level simulation and HDL designs of various radar and array processing algorithms.
      MATLAB
      •
      Other
      •15•0•0•0•Updated Oct 19, 2023Oct 19, 2023

    • rfsoc_frequency_planner

      Public
      An RFSoC Frequency Planner developed using Python.
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •7•0•0•0•Updated Oct 19, 2023Oct 19, 2023

    • wal

      Public
      WAL enables programmable waveform analysis.
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •18•0•0•0•Updated Oct 19, 2023Oct 19, 2023

    • openofdm

      Public
      Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
      Verilog
      •
      Apache License 2.0
      •188•0•0•0•Updated Oct 13, 2023Oct 13, 2023

    • blue-ethernet

      Public
      High-performance Ethernet components for FPGA implementation
      Bluespec
      •1•0•0•0•Updated Oct 6, 2023Oct 6, 2023

    • 100G-fpga-network-stack-core

      Public
      This repo contains the Limago code
      C++
      •
      Other
      •25•0•0•0•Updated Sep 18, 2023Sep 18, 2023

    • xup_vitis_network_example

      Public
      VNx: Vitis Network Examples
      Jupyter Notebook
      •
      Other
      •43•0•0•0•Updated Aug 31, 2023Aug 31, 2023

    • rfsoc_qsfp_offload

      Public
      RFSoC QSFP Data Offload Design with GNU Radio
      Tcl
      •7•0•0•0•Updated Aug 28, 2023Aug 28, 2023

    • GULF-Stream

      Public
      100G Udp Link For axi Stream
      Tcl
      •
      Other
      •12•0•0•0•Updated Aug 23, 2023Aug 23, 2023

    • rfsoc_sdfec

      Public
      Tcl
      •
      BSD 3-Clause "New" or "Revised" License
      •2•0•0•0•Updated Jul 31, 2023Jul 31, 2023

    • corundum

      Public
      Open source FPGA-based NIC and platform for in-network compute
      Verilog
      •
      Other
      •414•0•0•0•Updated Jul 17, 2023Jul 17, 2023

    • 10g-low-latency-ethernet

      Public
      10G Low Latency Ethernet
      SystemVerilog
      •
      MIT License
      •15•0•0•0•Updated Jul 15, 2023Jul 15, 2023

    • rfsoc_ofdm

      Public
      PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
      VHDL
      •16•0•0•0•Updated Mar 16, 2023Mar 16, 2023

    • matplotplusplus

      Public
      Matplot++: A C++ Graphics Library for Data Visualization 📊🗾
      C++
      •
      MIT License
      •327•0•0•0•Updated Feb 17, 2023Feb 17, 2023

    • SpinalHDL-ethernet

      Public
      Scala
      •1•0•0•0•Updated Feb 15, 2023Feb 15, 2023

    • maxas

      Public
      Assembler for NVIDIA Maxwell architecture
      Sass
      •
      MIT License
      •161•0•0•0•Updated Jan 3, 2023Jan 3, 2023

    • embeddedsw

      Public
      Xilinx Embedded Software (embeddedsw) Development (FMMU branch)
      sdkzynqfreertosxilinxvivadobsp
      HTML
      •
      Other
      •1.1k•0•0•0•Updated Nov 13, 2022Nov 13, 2022

    • Vitis_with_100Gbps_TCP-IP

      Public
      100 Gbps TCP/IP stack for Vitis shells
      C++
      •75•0•0•0•Updated Oct 24, 2022Oct 24, 2022

    • RFSoC4x2-BSP

      Public
      Tcl
      •6•0•0•0•Updated Sep 28, 2022Sep 28, 2022

    • DRFM

      Public
      Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"
      Verilog
      •12•0•0•0•Updated Dec 10, 2021Dec 10, 2021

    • DirectNVM

      Public
      An open-source RTL NVMe controller IP for Xilinx FPGA.
      VHDL
      •16•0•0•0•Updated Feb 25, 2021Feb 25, 2021

    • zed_vvm

      Public
      RF vector volt-meter: Zedboard, DC1525A daughter board, litex, debian
      Jupyter Notebook
      •1•0•0•0•Updated Nov 11, 2020Nov 11, 2020

    • INT_FP_MAC

      Public
      INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
      Verilog
      •
      MIT License
      •12•0•0•0•Updated Sep 27, 2020Sep 27, 2020

    • pychirpz

      Public
      Python and C++ implementation of the Chirp-Z transform
      Python
      •
      MIT License
      •7•0•0•0•Updated Aug 11, 2020Aug 11, 2020

    • GULF-Stream-2020

      Public
      C++
      •
      Other
      •3•0•0•0•Updated May 28, 2020May 28, 2020

    • lbus_axis_converter

      Public
      Lbus to AXI4-Stream converter in verilog
      Verilog
      •
      MIT License
      •3•0•0•0•Updated Mar 26, 2020Mar 26, 2020

    • recvmsg_vs_recvmmsg

      Public
      Test performance of recvmsg() and recvmmsg() system calls.
      C
      •2•0•0•0•Updated Jul 27, 2018Jul 27, 2018