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@RISC-Processor RISC-Processor

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    6 repositories

    • Pipelined-Processor-in-Vivado

      Public
      Pipelined Processor in Vivado for Simulation
      Verilog
      •0•0•0•0•Updated Dec 24, 2024Dec 24, 2024

    • Pipelined-Processor-In-DE2-115

      Public
      Python
      •
      MIT License
      •0•0•0•0•Updated Dec 24, 2024Dec 24, 2024

    • Processor-In-DE2-115

      Public
      Processor-In-DE2-115_V2
      Python
      •
      MIT License
      •0•0•0•0•Updated Dec 7, 2024Dec 7, 2024

    • Non-Pipelined-Processor

      Public
      Single cycle non-pipelined processor for RV32I
      Tcl
      •0•0•0•0•Updated Oct 24, 2024Oct 24, 2024

    • UART_Tx_Rx

      Public
      transmit instructions and receive the register file for debugging
      Python
      •0•0•0•0•Updated Oct 17, 2024Oct 17, 2024

    • Bit-Stream-Generator

      Public
      generate bit stream for given RISC RV32I instructions
      Python
      •
      MIT License
      •0•0•0•0•Updated Oct 17, 2024Oct 17, 2024