chore: add codespell lint

.codespellignore

@@ -0,0 +1,5 @@
+InOut
+inout
+LoadE
+SelectE
+ser

.github/workflows/lints.yml

@@ -20,6 +20,12 @@ jobs:
     steps:
       - uses: runs-on/action@v1
       - uses: actions/checkout@v4
+
+      - uses: codespell-project/actions-codespell@v2
+        with:
+          skip: Cargo.lock,./book/pnpm-lock.yaml,*.txt,./crates/toolchain/openvm/src/memcpy.s,./crates/toolchain/openvm/src/memset.s,
+          ignore_words_file: .codespellignore
+
       - uses: dtolnay/rust-toolchain@stable
       - uses: Swatinem/rust-cache@v2
         with:

crates/circuits/mod-builder/src/builder.rs

@@ -134,7 +134,7 @@ impl ExprBuilder {
         // We don't support multi-op chip that doesn't need setup right now.
         assert!(needs_setup || self.num_flags == 0);
 
-        // setup the defalut flag if needed
+        // setup the default flag if needed
         if needs_setup && self.num_flags == 0 {
             self.new_flag();
         }

crates/circuits/mod-builder/src/core_chip.rs

@@ -36,7 +36,7 @@ pub struct FieldExpressionCoreAir {
     pub local_opcode_idx: Vec<usize>,
     /// Opcode flag idx (indices from builder.new_flag()) for all except setup opcode. Empty if single op chip.
     pub opcode_flag_idx: Vec<usize>,
-    // Example 1: 1-op chip EcAdd that nees setup
+    // Example 1: 1-op chip EcAdd that needs setup
     //   local_opcode_idx = [0, 2], where 0 is EcAdd, 2 is setup
     //   opcode_flag_idx = [], not needed for single op chip.
     // Example 2: 1-op chip EvaluateLine that doesn't need setup

crates/circuits/primitives/src/README.md

@@ -22,10 +22,10 @@ The following modules contain `SubAir`'s:
 
 ## SubAir
 
-Trait with associated types intended to allow re-use of constraint logic inside other AIRs.
+Trait with associated types intended to allow reuse of constraint logic inside other AIRs.
 
 A `SubAir` is **not** an `Air` itself.
-It is a struct that holds the means to generate a particular set of constraints, meant to be re-usable within other AIRs.
+It is a struct that holds the means to generate a particular set of constraints, meant to be reusable within other AIRs.
 
 The trait is designed to be maximally flexible, but typical implementations will separate the `AirContext` into two parts: `Io` and `AuxCols`. 
 The `Io` part will consist of expressions (built using `AB::Expr`) that the `SubAir` does not own, while the `AuxCols` are any internal columns that the `SubAir` requires to generate its constraints. 

crates/circuits/primitives/src/assert_less_than/mod.rs

@@ -29,7 +29,7 @@ pub struct AssertLessThanIo<T> {
     /// by the subair.
     ///
     /// N.B.: in fact range checks could always be done, if the aux
-    /// subrow values are set to 0 when `count == 0`. This woud slightly
+    /// subrow values are set to 0 when `count == 0`. This would slightly
     /// simplify the range check interactions, although usually doesn't change
     /// the overall constraint degree. It however leads to the annoyance that
     /// you must update the RangeChecker's multiplicities even on dummy padding
@@ -66,7 +66,7 @@ pub struct LessThanAuxCols<T, const AUX_LEN: usize> {
 /// size `bus.range_max_bits`, and interacts with a
 /// `VariableRangeCheckerBus` to range check the decompositions.
 ///
-/// The SubAir will own auxilliary columns to store the decomposed limbs.
+/// The SubAir will own auxiliary columns to store the decomposed limbs.
 /// The number of limbs is `max_bits.div_ceil(bus.range_max_bits)`.
 ///
 /// The expected max constraint degree of `eval` is

crates/circuits/primitives/src/assert_less_than/tests.rs

@@ -97,7 +97,7 @@ impl<const AUX_LEN: usize> AssertLessThanChip<AUX_LEN> {
 
 #[test]
 fn test_borrow_mut_roundtrip() {
-    const AUX_LEN: usize = 2; // number of auxilliary columns is two
+    const AUX_LEN: usize = 2; // number of auxiliary columns is two
 
     let num_cols = AssertLessThanCols::<usize, AUX_LEN>::width();
     let mut all_cols = (0..num_cols).collect::<Vec<usize>>();

crates/circuits/primitives/src/is_less_than/mod.rs

@@ -31,7 +31,7 @@ pub struct IsLessThanIo<T> {
     /// by the subair.
     ///
     /// N.B.: in fact range checks could always be done, if the aux
-    /// subrow values are set to 0 when `count == 0`. This woud slightly
+    /// subrow values are set to 0 when `count == 0`. This would slightly
     /// simplify the range check interactions, although usually doesn't change
     /// the overall constraint degree. It however leads to the annoyance that
     /// you must update the RangeChecker's multiplicities even on dummy padding
@@ -58,7 +58,7 @@ impl<T> IsLessThanIo<T> {
 /// into limbs of size `bus.range_max_bits`, and interacts with a
 /// `VariableRangeCheckerBus` to range check the decompositions.
 ///
-/// The SubAir will own auxilliary columns to store the decomposed limbs.
+/// The SubAir will own auxiliary columns to store the decomposed limbs.
 /// The number of limbs is `max_bits.div_ceil(bus.range_max_bits)`.
 ///
 /// The expected max constraint degree of `eval` is

crates/circuits/primitives/src/sub_air.rs

@@ -1,11 +1,11 @@
 use openvm_stark_backend::p3_air::AirBuilder;
 
-/// Trait with associated types intended to allow re-use of constraint logic
+/// Trait with associated types intended to allow reuse of constraint logic
 /// inside other AIRs.
 ///
 /// A `SubAir` is **not** an [Air](openvm_stark_backend::p3_air::Air) itself.
 /// A `SubAir` is a struct that holds the means to generate a particular set of constraints,
-/// meant to be re-usable within other AIRs.
+/// meant to be reusable within other AIRs.
 ///
 /// The trait is designed to be maximally flexible, but typical implementations will separate
 /// the `AirContext` into two parts: `Io` and `AuxCols`. The `Io` part will consist of

crates/circuits/primitives/src/xor/lookup/mod.rs

@@ -41,7 +41,7 @@ pub struct XorLookupPreprocessedCols<T> {
 pub const NUM_XOR_LOOKUP_COLS: usize = size_of::<XorLookupCols<u8>>();
 pub const NUM_XOR_LOOKUP_PREPROCESSED_COLS: usize = size_of::<XorLookupPreprocessedCols<u8>>();
 
-/// Xor via preprocessed lookup table. Can only be used if inputs have less than appoximately 10-bits.
+/// Xor via preprocessed lookup table. Can only be used if inputs have less than approximately 10-bits.
 #[derive(Clone, Copy, Debug, derive_new::new)]
 pub struct XorLookupAir<const M: usize> {
     pub bus: XorBus,

crates/circuits/sha256-air/src/columns.rs

@@ -47,7 +47,7 @@ pub struct Sha256DigestCols<T> {
 #[repr(C)]
 #[derive(Clone, Copy, Debug, AlignedBorrow)]
 pub struct Sha256MessageScheduleCols<T> {
-    /// The message schedule words as 32-bit intergers
+    /// The message schedule words as 32-bit integers
     pub w: [[T; SHA256_WORD_BITS]; SHA256_ROUNDS_PER_ROW],
     /// Will be message schedule carries for rows 4..16 and a buffer for rows 0..4 to be used freely by wrapper chips
     /// Note: carries are represented as 2 bit numbers

crates/circuits/sha256-air/src/utils.rs

@@ -43,7 +43,7 @@ pub const SHA256_WIDTH: usize = if SHA256_ROUND_WIDTH > SHA256_DIGEST_WIDTH {
     SHA256_DIGEST_WIDTH
 };
 /// We can notice that `carry_a`'s and `carry_e`'s are always the same on invalid rows
-/// To optimize the trace generation of invalid rows, we have thos values precomputed here
+/// To optimize the trace generation of invalid rows, we have those values precomputed here
 pub(crate) const SHA256_INVALID_CARRY_A: [[u32; SHA256_WORD_U16S]; SHA256_ROUNDS_PER_ROW] = [
     [1230919683, 1162494304],
     [266373122, 1282901987],

crates/prof/src/aggregate.rs

@@ -17,7 +17,7 @@ pub struct GroupedMetrics {
 
 #[derive(Clone, Debug, Default, Serialize, Deserialize)]
 pub struct AggregateMetrics {
-    /// "group" label => metric aggregate statitics
+    /// "group" label => metric aggregate statistics
     #[serde(flatten)]
     pub by_group: HashMap<String, HashMap<MetricName, Stats>>,
     /// In seconds

crates/toolchain/platform/src/heap/bump.rs

@@ -18,7 +18,7 @@ unsafe impl GlobalAlloc for BumpPointerAlloc {
 
     unsafe fn alloc_zeroed(&self, layout: Layout) -> *mut u8 {
         // NOTE: This is safe to avoid zeroing allocated bytes, as the bump allocator does not
-        //       re-use memory and the zkVM memory is zero-initialized.
+        //       reuse memory and the zkVM memory is zero-initialized.
         self.alloc(layout)
     }
 }

crates/vm/src/arch/integration_api.rs

@@ -52,7 +52,7 @@ pub trait VmAdapterChip<F> {
     /// Given instruction, perform memory reads and return only the read data that the integrator needs to use.
     /// This is called at the start of instruction execution.
     ///
-    /// The implementor may choose to store data in the `Self::ReadRecord` struct, for example in
+    /// The implementer may choose to store data in the `Self::ReadRecord` struct, for example in
     /// an [Option], which will later be sent to the `postprocess` method.
     #[allow(clippy::type_complexity)]
     fn preprocess(

crates/vm/src/system/memory/offline_checker/bridge.rs

@@ -286,7 +286,7 @@ impl MemoryOfflineChecker {
     }
 
     /// At the core, eval_bulk_access is a bunch of push_sends and push_receives.
-    /// The max constraint degree of expressions in sends/recieves is:
+    /// The max constraint degree of expressions in sends/receives is:
     /// max(max_deg(data), max_deg(prev_data), max_deg(timestamp), max_deg(prev_timestamps))
     /// Also, each one of them has count with degree: deg(enabled)
     #[allow(clippy::too_many_arguments)]

extensions/algebra/guest/src/lib.rs

@@ -219,7 +219,7 @@ pub trait IntMod:
         let _ = core::hint::black_box(PartialEq::eq(self, self));
     }
 
-    /// This function is mostly for internal use in other internal implemntations.
+    /// This function is mostly for internal use in other internal implementations.
     /// Normal users are not advised to use it.
     ///
     /// If `self` was directly constructed from a raw representation

extensions/bigint/tests/programs/examples/matrix-power-signed.rs

@@ -68,7 +68,7 @@ pub fn main() {
     for i in 0..N {
         for j in 0..N {
             if c[i][j] != two_to_200 {
-                print("FAIL: the resulting matrix is incorect");
+                print("FAIL: the resulting matrix is incorrect");
                 panic!();
             }
         }

extensions/bigint/tests/programs/examples/matrix-power-unsigned.rs

@@ -68,7 +68,7 @@ pub fn main() {
     for i in 0..N {
         for j in 0..N {
             if c[i][j] != two_to_200 {
-                print("FAIL: the resulting matrix is incorect");
+                print("FAIL: the resulting matrix is incorrect");
                 panic!();
             }
         }

extensions/keccak256/circuit/src/air.rs

@@ -621,7 +621,7 @@ impl KeccakVmAir {
     }
 
     /// Amount to advance timestamp by after execution of one opcode instruction.
-    /// This is an upper bound dependant on the length `len` operand, which is unbounded.
+    /// This is an upper bound dependent on the length `len` operand, which is unbounded.
     pub fn timestamp_change<T: FieldAlgebra>(len: impl Into<T>) -> T {
         // actual number is ceil(len / 136) * (3 + 17) + KECCAK_DIGEST_WRITES
         // digest writes only done on last row of multi-block

extensions/keccak256/circuit/src/trace.rs

@@ -149,7 +149,7 @@ where
 
         let aux_cols_factory = memory.aux_cols_factory();
 
-        // Use unsafe alignment so we can parallely write to the matrix
+        // Use unsafe alignment so we can parallelly write to the matrix
         let mut trace =
             RowMajorMatrix::new(Val::<SC>::zero_vec(num_rows * trace_width), trace_width);
         let limb_shift_bits = RV32_CELL_BITS * RV32_REGISTER_NUM_LIMBS - self.air.ptr_max_bits;

extensions/native/circuit/src/fri/mod.rs

@@ -448,7 +448,7 @@ impl FriReducedOpeningAir {
             let mut is_ins_row = when_transition.when(local.general.is_ins_row);
             let mut not_first_ins_row = is_ins_row.when_ne(local.is_first, AB::Expr::ONE);
             // ATTENTION: degree of not_first_ins_row is 2
-            // Because all the followings assert 0, we don't need to check next.enabled.
+            // Because all the following assert 0, we don't need to check next.enabled.
             // The next row must be a workload row.
             not_first_ins_row.assert_zero(next.prefix.general.is_ins_row);
             // The next row must have idx = 0.

extensions/native/compiler/src/asm/compiler.rs

@@ -773,7 +773,7 @@ impl<F: PrimeField32 + TwoAdicField, EF: ExtensionField<F> + TwoAdicField> IfCom
         } = self;
 
         // Get the label for the current block, so we can generate the jump instruction into it.
-        // conditional branc instruction to it, if the condition is not met.
+        // conditional branch instruction to it, if the condition is not met.
         let if_branching_block = compiler.block_label();
 
         // Generate the block for the then branch.

extensions/native/compiler/src/constraints/halo2/baby_bear.rs

@@ -21,7 +21,7 @@ use snark_verifier_sdk::snark_verifier::{
 pub(crate) const BABYBEAR_MAX_BITS: usize = 31;
 // bits reserved so that if we do lazy range checking, we still have a valid result
 // the first reserved bit is so that we can represent negative numbers
-// the second is to accomodate lazy range checking
+// the second is to accommodate lazy range checking
 const RESERVED_HIGH_BITS: usize = 2;
 
 #[derive(Copy, Clone, Debug)]

extensions/native/compiler/src/ir/utils.rs

@@ -13,8 +13,8 @@ pub const LIMB_BITS: usize = 8;
 
 /// Converts a prime field element to a usize.
 pub fn prime_field_to_usize<F: PrimeField>(x: F) -> usize {
-    let bu = x.as_canonical_biguint();
-    let digits = bu.to_u64_digits();
+    let biguint = x.as_canonical_biguint();
+    let digits = biguint.to_u64_digits();
     if digits.is_empty() {
         return 0;
     }

extensions/native/compiler/tests/poseidon2.rs

@@ -23,7 +23,7 @@ fn test_compiler_poseidon2_permute() {
     let perm = default_perm();
     let expected_result = perm.permute(random_state_vals);
 
-    // Execture the permutation in the VM
+    // Execute the permutation in the VM
     // Initialize an array and populate it with the entries.
     let var_width: Var<F> = builder.eval(F::from_canonical_usize(PERMUTATION_WIDTH));
     let random_state = builder.array(var_width);

extensions/native/recursion/src/fri/domain.rs

@@ -225,7 +225,7 @@ pub(crate) mod tests {
 
             let log_quotient_degree = 2;
 
-            // Initialize a reference doamin.
+            // Initialize a reference domain.
             let domain_val = natural_domain_for_degree(1 << log_d_val);
             let domain = builder.constant(domain_val);
 
@@ -257,7 +257,7 @@ pub(crate) mod tests {
                 zeta_val,
             );
 
-            // Now try splited domains
+            // Now try split domains
             let qc_domains_val = disjoint_domain_val.split_domains(1 << log_quotient_degree);
             for dom_val in qc_domains_val.iter() {
                 let dom = builder.constant(*dom_val);

extensions/native/recursion/src/fri/two_adic_pcs.rs

@@ -338,11 +338,11 @@ where
         let mats = builder
             .dyn_array::<TwoAdicPcsMatsVariable<C>>(RVar::from(domains_and_openings_val.len()));
 
-        for (i, (domain, openning)) in domains_and_openings_val.into_iter().enumerate() {
+        for (i, (domain, opening)) in domains_and_openings_val.into_iter().enumerate() {
             let domain = builder.constant::<TwoAdicMultiplicativeCosetVariable<_>>(domain);
 
-            let points_val = openning.iter().map(|(p, _)| *p).collect::<Vec<_>>();
-            let values_val = openning.iter().map(|(_, v)| v.clone()).collect::<Vec<_>>();
+            let points_val = opening.iter().map(|(p, _)| *p).collect::<Vec<_>>();
+            let values_val = opening.iter().map(|(_, v)| v.clone()).collect::<Vec<_>>();
             let points: Array<_, Ext<_, _>> = builder.dyn_array(points_val.len());
             for (j, point) in points_val.into_iter().enumerate() {
                 let el: Ext<_, _> = builder.eval(point.cons());

extensions/rv32-adapters/src/heap_branch.rs

@@ -115,7 +115,7 @@ impl<AB: InteractionBuilder, const NUM_READS: usize, const READ_SIZE: usize> VmA
             1 << (RV32_CELL_BITS * RV32_REGISTER_NUM_LIMBS - self.address_bits),
         );
 
-        // Note: since limbs are read from memory we alread know that limb[i] < 2^RV32_CELL_BITS
+        // Note: since limbs are read from memory we already know that limb[i] < 2^RV32_CELL_BITS
         //       thus range checking limb[i] * shift < 2^RV32_CELL_BITS, gives us that
         //       limb[i] < 2^(addr_bits - (RV32_CELL_BITS * (RV32_REGISTER_NUM_LIMBS - 1)))
         for pair in need_range_check.chunks(2) {

extensions/rv32-adapters/src/vec_heap.rs

@@ -260,7 +260,7 @@ impl<
             1 << (RV32_CELL_BITS * RV32_REGISTER_NUM_LIMBS - self.address_bits),
         );
 
-        // Note: since limbs are read from memory we alread know that limb[i] < 2^RV32_CELL_BITS
+        // Note: since limbs are read from memory we already know that limb[i] < 2^RV32_CELL_BITS
         //       thus range checking limb[i] * shift < 2^RV32_CELL_BITS, gives us that
         //       limb[i] < 2^(addr_bits - (RV32_CELL_BITS * (RV32_REGISTER_NUM_LIMBS - 1)))
         for pair in need_range_check.chunks_exact(2) {

extensions/rv32-adapters/src/vec_heap_two_reads.rs

@@ -282,7 +282,7 @@ impl<
             1 << (RV32_CELL_BITS * RV32_REGISTER_NUM_LIMBS - self.address_bits),
         );
 
-        // Note: since limbs are read from memory we alread know that limb[i] < 2^RV32_CELL_BITS
+        // Note: since limbs are read from memory we already know that limb[i] < 2^RV32_CELL_BITS
         //       thus range checking limb[i] * shift < 2^RV32_CELL_BITS, gives us that
         //       limb[i] < 2^(addr_bits - (RV32_CELL_BITS * (RV32_REGISTER_NUM_LIMBS - 1)))
         for pair in need_range_check.chunks_exact(2) {

extensions/rv32im/circuit/src/adapters/loadstore.rs

@@ -54,17 +54,17 @@ pub struct LoadStoreInstruction<T> {
     pub opcode: T,
     pub is_load: T,
 
-    /// Keeping two seperate shift amounts is needed for getting the read_ptr/write_ptr with degree 2
+    /// Keeping two separate shift amounts is needed for getting the read_ptr/write_ptr with degree 2
     /// load_shift_amount will be the shift amount if load and 0 if store
     pub load_shift_amount: T,
     /// store_shift_amount will be 0 if load and the shift amount if store
     pub store_shift_amount: T,
 }
 
-/// The LoadStoreAdapter seperates Runtime and Air AdapterInterfaces.
+/// The LoadStoreAdapter separates Runtime and Air AdapterInterfaces.
 /// This is necessary because `prev_data` should be owned by the core chip and sent to the adapter,
 /// and it must have an AB::Var type in AIR as to satisfy the memory_bridge interface.
-/// This is achived by having different types for reads and writes in Air AdapterInterface.
+/// This is achieved by having different types for reads and writes in Air AdapterInterface.
 /// This method ensures that there are no modifications to the global interfaces.
 ///
 /// Here 2 reads represent read_data and prev_data,

extensions/rv32im/circuit/src/loadstore/core.rs

@@ -40,7 +40,7 @@ use InstructionOpcode::*;
 /// LoadStore Core Chip handles byte/halfword into word conversions and unsigned extends
 /// This chip uses read_data and prev_data to constrain the write_data
 /// It also handles the shifting in case of not 4 byte aligned instructions
-/// This chips treats each (opcode, shift) pair as a seperate instruction
+/// This chips treats each (opcode, shift) pair as a separate instruction
 #[repr(C)]
 #[derive(Debug, Clone, AlignedBorrow)]
 pub struct LoadStoreCoreCols<T, const NUM_CELLS: usize> {