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Merge branch 'master' into um_hdrs
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@MikeOpenHWGroup
MikeOpenHWGroup authored Dec 14, 2020
2 parents 86ba2cf + c45466f commit cffcded
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8 changes: 5 additions & 3 deletions cores/cv32e40p/user_manual/source/core_versions.rst
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Expand Up @@ -100,9 +100,11 @@ Following, all the GitHub tags related to ``mimpid=0``.
+--------------------+-------------------+------------+--------------------+---------+
| Git Tag | Tagged By | Date | Reason for Release | Comment |
+====================+===================+============+====================+=========+
| cv32e40p_v1.0.0 | | yyyy-mm-dd | | |
| cv32e40p_v1.0.0 | Arjan Bink | 2020-12-10 | RTL Freeze | |
+--------------------+-------------------+------------+--------------------+---------+

The list of open (waived) issues at the time of applying the cv32e40p_v1.0.0 tag can be found at:

At the time of applying the cv32e40p_v1.0.0 tag, there are 277 closed issues and 48 WAIVED open-issues for the given parameters, and the most recent known github issue was https://github.com/openhwgroup/cv32e40p/issues/598.
The list of open-issues can be found at https://github.com/openhwgroup/core-v-docs/blob/master/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Design_openissues.md .
* https://github.com/openhwgroup/core-v-docs/blob/master/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Design_openissues.md
* https://github.com/openhwgroup/core-v-docs/blob/master/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Verification_openissues.md
* https://github.com/openhwgroup/core-v-docs/blob/master/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Documentation_openissues.md
9 changes: 2 additions & 7 deletions program/milestones/CV32E40P/RTL_Freeze_v1.0.0/DesignChecklist.md
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Expand Up @@ -4,7 +4,7 @@ An item is "signed off" once the `Signed-off By` and `Sign-off Date` cells are f

| Category | Item | Sign-off Criteria | Signed-off By | Sign-off Date | Exceptions/Waivers/Comments |
| ---------------- | ------------------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | --------------------- | ---------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| Configuration | Version clearly identified | The version at this release is clearly identified in GitHub and in the RTL freeze review document. | arjan.bink@silabs.com | 2020-12-02 | The CV32E40P RTL Freeze version is at https://github.com/openhwgroup/cv32e40p with git hash 6fa35456a7cec2687a5ef2683deff2ee6699d69c and tag cv32e40p_v1.0.0 |
| Configuration | Version clearly identified | The version at this release is clearly identified in GitHub and in the RTL freeze review document. | arjan.bink@silabs.com | 2020-12-10 | The CV32E40P RTL Freeze version is at https://github.com/openhwgroup/cv32e40p with git hash 120ac3ee79ef56a57fe07dd8701cd4ee94458fd5 and tag cv32e40p_v1.0.0 |
| Coding rules | Module and File names | No two modules in the design have the same name. Each module name shall be prefixed with the project name (e.g. cv32e40p_<module>) Each module name shall match the file name using the system verilog suffix ".sv" (e.g. cv32e40p_controller module located in cv32e40p_controller.sv file) Each system verilog file shall contain only one module definition | davide@openhwgroup.org | 2020-12-02 | Except for the cv32e40p_register_file who is defined both in the cv3240p_register_file_ff.sv and cv32e40p_register_file_latch.sv file. Only one can be compiled. By default the ff version is selected as reported in the manifest file. |
| Coding rules | Implementation HDL | The design does not mix HDLs. | davide@openhwgroup.org | 2020-12-02 | |
| Coding rules | Low technology dependence | In IP designs, technology-specific blocks (mainly RAM cells) are accessible and easily replaced by blocks targetting other ASIC or FPGA technologies. | davide@openhwgroup.org | 2020-12-02 | The cv32e40p_sim_clock_gate.sv does not contain a tech-specific block. The user needs to replace it with a tech-specific clock gating cell |
Expand All @@ -25,9 +25,4 @@ An item is "signed off" once the `Signed-off By` and `Sign-off Date` cells are f
| Design rules | Reset fanout | Same type of reset in the whole design (synchronous/asynchronous, active high/low) | davide@openhwgroup.org | 2020-12-02 | |
| Design rules | FSM reset | FSM state register has a reset | davide@openhwgroup.org | 2020-12-02 | |
| Design rules | No tri-state | No internal tri-state buffers | davide@openhwgroup.org | 2020-12-02 | Does not apply to I/O pads. |
| Synthesizable IP | Linting | A linting tool was used; it reports no error and all outstanding warnings can be waived. | arjan.bink@silabs.com | 2020-12-02 | |
| Open-source | Third-party audit | Eclipse “CQ” audit complete | mike@openhwgroup.org | 2020-11-18 | https://dev.eclipse.org/ipzilla/show_bug.cgi?id=22415 |
| Open-source | No closed-source | All RTL code in the design is open-source. It includes the appropriate licence notices. | davide@openhwgroup.org | 2020-12-03 | |
| Open-source | OpenHW design licence | OpenHW Group RTL source code is under the Solderpad 0.51 or 2.0 licence | davide@openhwgroup.org | 2020-12-03 | |
| Open-source | Third-party IP licence | Third party IP licence terms do not contaminate other designs in the modules and do not prevent to use the design in closed-source projects (e.g. GPL IP cannot be integrated in OpenHW projects). | | | |
| Open-source | No export restrictions | Contributions do not include controlled software or technology or other information that is subject to export control laws and regulations in any applicable jurisdictions, including but not limited to U.S. Export Administration Regulations (15 CFR Chapter VII, Subchapter C, Parts 730-744, EAR). [Excerpt from OpenHW Group Membership Agreement] OpenHW members are bound to this agreement; the use of external IP is not. | | | |
| Synthesizable IP | Linting | A linting tool was used; it reports no error and all outstanding warnings can be waived. | arjan.bink@silabs.com | 2020-12-10 | |
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