Expected behavior with an erroneous test

[pcotret]

I was trying to see what should be the output of the simulation with an erroneous test. Steps:

1. Modify a riscv-test and insert an error. For instance, in rv64ui/and.S:

  TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0xdeadbeef );

2. Recompile the riscv-tests suite
3. Execute the Verilator simulation

$ ./work-ver/Variane_testharness tmp/riscv-tests/build/isa/rv64ui-p-and
This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.
Listening on port 42003
- /home/pascal/cva6-experiments/cva6/corev_apu/tb/rvfi_tracer.sv:56: Verilog $finish
- /home/pascal/cva6-experiments/cva6/corev_apu/tb/rvfi_tracer.sv:57: Verilog $finish
- /home/pascal/cva6-experiments/cva6/corev_apu/tb/rvfi_tracer.sv:57: Second verilog $finish, exiting

I was expecting to get an error related to my step 1 (yes, I made sure to use my freshly compiled binary). Am I doing something wrong?

[pcotret]

Nevermind, same solution as for issue #748