Pll

Makefile

@@ -125,16 +125,16 @@ nexys-emul:
 				@echo "*                                   *"
 				@echo "*************************************"
 				mkdir -p emulation/core-v-mcu-nexys/rtl
-				python3 util/ioscript.py\
-					--soc-defines rtl/includes/pulp_soc_defines.svh\
-					--peripheral-defines rtl/includes/pulp_peripheral_defines.svh\
-					--periph-bus-defines rtl/includes/periph_bus_defines.svh\
-					--pin-table nexys-pin-table.csv\
-					--perdef-json perdef.json\
-					--pad-control rtl/core-v-mcu/top/pad_control.sv\
-					--emulation-toplevel core_v_mcu_nexys\
-					--xilinx-core-v-mcu-sv emulation/core-v-mcu-nexys/rtl/core_v_mcu_nexys.v\
-					--input-xdc emulation/core-v-mcu-nexys/constraints/Nexys-A7-100T-Master.xdc\
+				python3 util/ioscript.py \
+					--soc-defines rtl/includes/pulp_soc_defines.svh \
+					--peripheral-defines rtl/includes/pulp_peripheral_defines.svh \
+					--periph-bus-defines rtl/includes/periph_bus_defines.svh \
+					--pin-table nexys-pin-table.csv \
+					--perdef-json perdef.json \
+					--pad-control rtl/core-v-mcu/top/pad_control.sv \
+					--emulation-toplevel core_v_mcu_nexys \
+					--input-xdc emulation/core-v-mcu-nexys/constraints/Nexys-A7-100T-Master.xdc \
+		                        --xilinx-core-v-mcu-sv emulation/core-v-mcu-nexys/rtl/core_v_mcu_util.v \
 					--output-xdc emulation/core-v-mcu-nexys/constraints/core-v-mcu-pin-assignment.xdc
 				util/format-verible
 				@echo "*************************************"
@@ -210,6 +210,7 @@ ${IOSCRIPT_OUT}:	${IOSCRIPT}
 					--peripheral-defines rtl/includes/pulp_peripheral_defines.svh\
 					--periph-bus-defines rtl/includes/periph_bus_defines.svh\
 					--perdef-json perdef.json\
+					--pin-table nexys-pin-table.csv \
 					--pad-control rtl/core-v-mcu/top/pad_control.sv\
 					--xilinx-core-v-mcu-sv emulation/core-v-mcu-nexys/rtl/core_v_mcu_nexys.v\
 					--input-xdc emulation/core-v-mcu-nexys/constraints/Nexys-A7-100T-Master.xdc\

core-v-mcu-emul.core

@@ -1,4 +1,9 @@
 CAPI=2:
+
+# Copyright 2021 OpenHW Group
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
 name: openhwgroup.org:systems:core-v-mcu-emul
 description: CORE-V MCU Emulation Top.
 filesets:

core-v-mcu.core

@@ -1,4 +1,9 @@
 CAPI=2:
+
+# Copyright 2021 OpenHW Group
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
 name: openhwgroup.org:systems:core-v-mcu
 description: CORE-V MCU Top.
 filesets:
@@ -11,7 +16,6 @@ filesets:
     - pulp-platform.org::fpnew
     - pulp-platform.org::fpu_div_sqrt_mvp
     - openhwgroup.org:ip:apb_adv_timer
-    - openhwgroup.org:ip:apb_fll_if
     - openhwgroup.org:ip:apb_gpio
     - openhwgroup.org:ip:apb_i2cs
     - openhwgroup.org:ip:apb_node
@@ -30,7 +34,6 @@ filesets:
     - openhwgroup.org:ip:logint_dc_fifo_xbar
     - openhwgroup.org:ip:l2_tcdm_hybrid_interco
     - quicklogic.com:ip:efpga
-#    - openhwgroup.org:ip:generic_fll
     - openhwgroup.org:ip:tcdm_interconnect
     - openhwgroup.org:ip:cv32e40p
     files:
@@ -40,7 +43,6 @@ filesets:
     - rtl/includes/soc_mem_map.svh: {is_include_file: true, include_path: rtl/includes}
     - rtl/core-v-mcu/include/tcdm_macros.svh: {is_include_file: true, include_path: rtl/core-v-mcu/include/}
     - rtl/core-v-mcu/soc/pkg_soc_interconnect.sv
-#    - rtl/core-v-mcu/soc/axi64_2_lint32_wrap.sv
     - rtl/core-v-mcu/soc/lint_2_axi_wrap.sv
     - rtl/core-v-mcu/soc/contiguous_crossbar.sv
     - rtl/core-v-mcu/soc/interleaved_crossbar.sv
@@ -49,8 +51,8 @@ filesets:
     - rtl/core-v-mcu/soc/l2_ram_multi_bank.sv
     - rtl/core-v-mcu/soc/lint_jtag_wrap.sv
     - rtl/core-v-mcu/soc/periph_bus_wrap.sv
-    - rtl/core-v-mcu/soc/soc_clk_rst_gen.sv
-    - rtl/core-v-mcu/soc/clk_and_control.sv
+#    - rtl/core-v-mcu/soc/soc_clk_rst_gen.sv
+#    - rtl/core-v-mcu/soc/clk_and_control.sv
     - rtl/core-v-mcu/soc/soc_event_arbiter.sv
     - rtl/core-v-mcu/soc/soc_event_generator.sv
     - rtl/core-v-mcu/soc/soc_event_queue.sv
@@ -82,7 +84,7 @@ filesets:
     file_type: systemVerilogSource
   rtl-simulation:
     files:
-    - rtl/simulation/pPLL02F.sv
+    - rtl/simulation/PLL18_TOP.sv
     - rtl/simulation/core_v_mcu_sim_ram.sv
     - rtl/simulation/sram512x64.v
     - rtl/simulation/top.sv
@@ -91,22 +93,20 @@ filesets:
     file_type: systemVerilogSource
   not_emulation-rtl:
     files:
-    - rtl/core-v-mcu/soc/clk_gen.sv
+    - rtl/apb_fll_if/apb_pll.sv
     file_type: systemVerilogSource
   emulation-rtl:
     depend:
     - pulp-platform.org::tech_cells_xilinx
     files:
     - emulation/xilinx/rtl/cv32e40p_clock_gate.sv
-
+    - emulation/xilinx/rtl/fpga_pll.sv
     - emulation/xilinx/rtl/fpga_interleaved_ram.sv
     - emulation/xilinx/rtl/fpga_private_ram.sv
-    - emulation/xilinx/rtl/fpga_slow_clk_gen.sv
     - emulation/xilinx/rtl/pad_functional_xilinx.sv
     - emulation/xilinx/rtl/pulp_clock_gating_xilinx.sv
     - emulation/xilinx/rtl/sram512x64.v
     - emulation/xilinx/rtl/DW02_mac.sv
-    - rtl/simulation/pPLL02F.sv
     - rtl/simulation/top.sv
     - rtl/simulation/top1_wrapper.sv
     - rtl/simulation/a2_bootrom.sv
@@ -174,16 +174,20 @@ filesets:
   genesys2-rtl:
     files:
     - emulation/core-v-mcu-genesys2/rtl/core_v_mcu_genesys2.v
-    - emulation/core-v-mcu-genesys2/rtl/fpga_clk_gen.sv
+    - emulation/xilinx/rtl/fpga_clk_gen.sv
+#    - emulation/core-v-mcu-genesys2/rtl/fpga_clk_gen.sv
     file_type: systemVerilogSource
   genesys2-xdc:
     files:
     - emulation/core-v-mcu-genesys2/constraints/core-v-mcu-pin-assignment.xdc
     file_type: xdc
+
+  # Scripts for hooks
   pre_build_scripts:
     files:
     - rtl/core-v-mcu/scripts/vedit.sh
     file_type: user
+  # Waiver file, without which the model lib will not build.
   verilator-waiver:
     files:
     - rtl/core-v-mcu/verilator.waiver
@@ -201,6 +205,9 @@ parameters:
     datatype: bool
     paramtype: vlogdefine
     default: true
+
+# A script to modify Verilator pre-build to generate a library, not an
+# executable.
 scripts:
   pre_build_scripts:
     cmd:
@@ -212,7 +219,7 @@ targets:
   default: &default_target
     filesets:
     - files_rtl_generic
-    - not_emulation-rtl
+#    - not_emulation-rtl
     - target_lint? (rtl-behavioral)
     - target_model-lib? (rtl-behavioral)
     toplevel: [core_v_mcu]

emulation/core-v-mcu-genesys2/constraints/core-v-mcu-pin-assignment.xdc

@@ -18,8 +18,8 @@ set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { xilinx_i
 
 ## LEDs
 set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[11] }]; #IO_L11N_T1_SRCC_14 Sch=led[0]
-#set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
-#set_property -dict { PACKAGE_PIN U30   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
+set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[21] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
+set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[29] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
 #set_property -dict { PACKAGE_PIN U29   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3]
 #set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4]
 #set_property -dict { PACKAGE_PIN V26   IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5]
@@ -164,7 +164,7 @@ set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { xilinx_i
 set_property -dict { PACKAGE_PIN U23 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[44] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jb_n[4]
 
 ## PMOD Header JC
-set_property -dict { PACKAGE_PIN AC26 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[21] }]; #IO_L19P_T3_13 Sch=jc[1]
+#set_property -dict { PACKAGE_PIN AC26  IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19P_T3_13 Sch=jc[1]
 set_property -dict { PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[22] }]; #IO_L20P_T3_13 Sch=jc[2]
 set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[23] }]; #IO_L18N_T2_13 Sch=jc[3]
 set_property -dict { PACKAGE_PIN AK29 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[24] }]; #IO_L15P_T2_DQS_13 Sch=jc[4]
@@ -174,7 +174,7 @@ set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS33 } [get_ports { xilinx_
 set_property -dict { PACKAGE_PIN AK28 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[28] }]; #IO_L20N_T3_13 Sch=jc[10]
 
 ## PMOD Header JD
-set_property -dict { PACKAGE_PIN V27 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[29] }]; #IO_L16N_T2_A15_D31_14 Sch=jd[1]
+#set_property -dict { PACKAGE_PIN V27   IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L16N_T2_A15_D31_14 Sch=jd[1]
 set_property -dict { PACKAGE_PIN Y30 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[30] }]; #IO_L8P_T1_13 Sch=jd[2]
 set_property -dict { PACKAGE_PIN V24 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[31] }]; #IO_L23N_T3_A02_D18_14 Sch=jd[3]
 set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[32] }]; #IO_L24N_T3_A00_D16_14 Sch=jd[4]