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* Update efpga_subsystem.rst

* Update efpga_subsystem.rst

* Update efpga_subsystem.rst

* Update efpga_subsystem.rst

* Update efpga_subsystem.rst

* Update efpga_subsystem.rst

* Update efpga_subsystem.rst

* Update efpga_subsystem.rst

* Update efpga_subsystem.rst

* Update efpga_subsystem.rst

* Update efpga_subsystem.rst

* Update efpga_subsystem.rst

* Added Math block diagram

* Update efpga_subsystem.rst
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gmartin102 committed Jul 4, 2023
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116 changes: 99 additions & 17 deletions docs/doc-src/efpga_subsystem.rst
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Expand Up @@ -40,41 +40,96 @@ The eFPGA block

Math Units
^^^^^^^^^^
The EFPGA has 2 Math units attached. Each math unit has 3 block RAMS (4KBytes) and 2 Multipliers.
Each Block RAM has one read port and one write port with independant clocks. Each Port can be independenly configured as 8-bit, 16-bit or 32-bit by the configuration on the appropriate rmode, or wmode inputs.
The Write data can also be selected to be from the fabric or the output of the Associated Multiplier.


.. figure:: ../images/A2_MATH_UNIT.png
:name: MATH Unit Diagram
:align: center
:alt:

Block RAM
^^^^^^^^^

FIFO Controller
^^^^^^^^^^^^^^^

Clocking
^^^^^^^^
The eFPGA recieves 6 clocks from the SOC.

- Clk0 is sourced by the PLL and the eFPGA divisor Circuit.
- CLK1 is sources by the PLL and the peripheral divisor Circuit.
- CLK2 is sourced by the RefClock divisor Circut.
- CLK3 is source by an IO pin.
- CLK4 is sourced by an IO pin.
- CLK5 is sourced by an IO pin.


SoC Interfaces
--------------

Configurable Input/Output Signals
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The example RTL file top.sv in the rtl/simulation folder is functional rtl design for verifying the eFPGA interfaces.
It contain the mapping from the eFPGA to the SoC and IO. The example design instantiates all the interfaces and has simple logic that allows for exercising the interfaces, The various registers allow for control of all the resources and interfaces with simple state machines to demostrate the use of the resources.

APB Interface
L2 Interface
~~~~~~~~~~~~~
The L2 interface to the eFPGA is a memory mapped interface that is allocated a 1Mbyte address space.
It is asynchronous to the CPU and contains clock crossing registers to maintain data integrity.
the following table contains the L2 Interface signals. Various control registers are accessible via the L2 interface to test other functions in the eFPGA.

+------------+-----------------+---------------------------+
| direction | Name | Description. |
+============+=================+===========================+
| input | lint_REQ | Cycle request active high|
+------------+-----------------+---------------------------+
| input | lint_WEN | Write = 1, Read = 0. |
+------------+-----------------+---------------------------+
| input | lint_ADDR[19:0] | Address 20-bits |
+------------+-----------------+---------------------------+
| input | lint_WDATA[31:0]| Write Data 32-bits |
+------------+-----------------+---------------------------+
| input | lint_BE[3:0] | Byte enables 4-bits. |
+------------+-----------------+---------------------------+
| output | lint_VALID | Valid signal (ack) |
+------------+-----------------+---------------------------+
| output | lint_GNT | Grant signal |
+------------+-----------------+---------------------------+
| output | lint_RDATA[31:0]| Read Data 32-bits |
+------------+-----------------+---------------------------+
| output | lint_clk | Clock back to CDC logic |
+------------+-----------------+---------------------------+

TCDM Interface
~~~~~~~~~~~~~~

Interrupts
~~~~~~~~~~


eFPGA Bitstream Loading
-----------------------

eFPGA Configuration Control
~~~~~~~~~~~~~~~~~~~~~~~~~~~

eFPGA Template
~~~~~~~~~~~~~~
Core-v-mcu provides 4 TCDM (Tightly Coupled Distributed memory) Each of the these interfaces has full access to the 512KB of SoC memory allowing
the eFPGA to perform reads and writes to memory. Each interface is connected through Clock Domain Crossing registers as the eFPGA is clocked by
asynchronously from the SoC.

+-----------+----------------------+--------------------------------------------------+
| Direction | Name | Description |
+===========+======================+==================================================+
| output | tcdm_addr_p0[19:0] | 20-bit address for TCDM |
+-----------+----------------------+--------------------------------------------------+
| input | tcdm_rdata_p0[31:0] | 32-bit Read data returned from TCDM |
+-----------+----------------------+--------------------------------------------------+
| input | tcdm_valid_p0 | TCDM read data Valid |
+-----------+----------------------+--------------------------------------------------+
| input | tcdm_gnt_p0 | TCDM Grant indicating the cycle is in progress |
+-----------+----------------------+--------------------------------------------------+
| input | tcdm_fmo_p0 | TCDM interface can accept only one more request |
+-----------+----------------------+--------------------------------------------------+
| output | tcdm_wdata_p0[31:0] | 32-bit Data to write to TCDM |
+-----------+----------------------+--------------------------------------------------+
| output | tcdm_be_p0[3:0] | 4 byte enables for byte writes |
+-----------+----------------------+--------------------------------------------------+
| output | tcdm_wen_p0 | Write enable active high |
+-----------+----------------------+--------------------------------------------------+
| output | tcdm_req_p0 | TCDM cycle request |
+-----------+----------------------+--------------------------------------------------+
| output | tcdm_clk_p0 | TCDM clock from eFPGA to CDC logic |
+-----------+----------------------+--------------------------------------------------+


eFPGA Subsystem Registers
Expand Down Expand Up @@ -144,6 +199,8 @@ TCDM_CTL_P3 offset = 0x0C
| tcdm_addr_p3 | 19:0 | RW | 0x0 | Sets the address to be used on TCDM 3 |
+--------------+-------+------+------------+-------------------------------------------------------------+

There are 4 control regsisters (1 for each of te multiplier units) the bits in these registers will configure the multipler operation.

M0_M0_CONTROL offset = 0x10
~~~~~~~~~~~~~~~~~~~~~~~~~~~

Expand Down Expand Up @@ -236,29 +293,41 @@ M1_M1_CONTROL offset = 0x1C
| m1_m1_outsel | 5:0 | RW | 0x0 | Math Unit 1, Mutliplier 1 output select |
+--------------+-------+------+------------+---------------------------------------------------------------------------------+

Two RAM control registers are provide to configure the RAMs (1 for each Math unit)


M0_RAM_CONTROL offset = 0x20
~~~~~~~~~~~~~~~~~~~~~~~~~~~~

+----------------+-------+------+------------+-----------------------------------------------+
| Field | Bits | Type | Default | Description |
+================+=======+======+============+===============================================+
| m0_coef_wdsel | 14:14 | RW | 0x0 | Math Unit 0 coefficient RAM write data select |
| | | | | 0 = Fabric, 1 = Multipler output |
+----------------+-------+------+------------+-----------------------------------------------+
| m0_oper1_wdsel | 13:13 | RW | 0x0 | Math Unit 0 Operand 0 RAM write data select |
| | | | | 0 = Fabric, 1 = Multipler output |
+----------------+-------+------+------------+-----------------------------------------------+
| m0_oper0_wdsel | 12:12 | RW | 0x0 | Math Unit 0 Operand 1 RAM write data select |
| | | | | 0 = Fabric, 1 = Multipler output |
+----------------+-------+------+------------+-----------------------------------------------+
| m0_coef_wmode | 11:10 | RW | 0x0 | Math Unit 0 coefficient RAM write mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+
| m0_coef_rmode | 9:8 | RW | 0x0 | Math Unit 0 coefficient RAM read mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+
| m0_oper1_wmode | 7:6 | RW | 0x0 | Math Unit 0 operand 0 RAM write mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+
| m0_oper1_rmode | 5:4 | RW | 0x0 | Math Unit 0 operand 0 RAM read mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+
| m0_oper0_wmode | 3:2 | RW | 0x0 | Math Unit 0 operand 1 RAM write mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+
| m0_oper0_rmode | 1:0 | RW | 0x0 | Math Unit 0 operand 1 RAM read mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+

M1_RAM_CONTROL offset = 0x24
Expand All @@ -268,24 +337,37 @@ M1_RAM_CONTROL offset = 0x24
| Field | Bits | Type | Default | Description |
+================+=======+======+============+===============================================+
| m1_coef_wdsel | 14:14 | RW | 0x0 | Math Unit 1 coefficient RAM write data select |
| | | | | 0 = Fabric, 1 = Multipler output |
+----------------+-------+------+------------+-----------------------------------------------+
| m1_oper1_wdsel | 13:13 | RW | 0x0 | Math Unit 1 Operand 0 RAM write data select |
| | | | | 0 = Fabric, 1 = Multipler output |
+----------------+-------+------+------------+-----------------------------------------------+
| m1_oper0_wdsel | 12:12 | RW | 0x0 | Math Unit 1 Operand 1 RAM write data select |
| | | | | 0 = Fabric, 1 = Multipler output |
+----------------+-------+------+------------+-----------------------------------------------+
| m1_coef_wmode | 11:10 | RW | 0x0 | Math Unit 1 coefficient RAM write mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+
| m1_coef_rmode | 9:8 | RW | 0x0 | Math Unit 1 coefficient RAM read mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+
| m1_oper1_wmode | 7:6 | RW | 0x0 | Math Unit 1 operand 0 RAM write mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+
| m1_oper1_rmode | 5:4 | RW | 0x0 | Math Unit 1 operand 0 RAM read mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+
| m1_oper0_wmode | 3:2 | RW | 0x0 | Math Unit 1 operand 1 RAM write mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+
| m1_oper0_rmode | 1:0 | RW | 0x0 | Math Unit 1 operand 1 RAM read mode |
| | | | | 00 = 32-bit, 01 = 16=bit 10 = 8=bit |
+----------------+-------+------+------------+-----------------------------------------------+


Four clock enable registers that are write only and clear to zero, when written to a '1' and single
clock enable will be generated to the specified multiplier.

M0_M0_CLKEN offset = 0x30
~~~~~~~~~~~~~~~~~~~~~~~~~

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