.

nrf-hal-common/src/adc.rs

@@ -1,4 +1,4 @@
-//! API for the Analog to Digital converter
+//! API for the Analog to Digital converter.
 
 use embedded_hal::adc::{Channel, OneShot};
 
@@ -63,7 +63,7 @@ pub struct AdcConfig {
     pub reference: Reference,
 }
 
-// 0 volts reads as 0, VDD volts reads as 2^10
+// 0 volts reads as 0, VDD volts reads as 2^10.
 impl Default for AdcConfig {
     fn default() -> Self {
         Self {

nrf-hal-common/src/clocks.rs

@@ -1,5 +1,4 @@
-//! Configuration and control of the High and Low Frequency Clock
-//! sources
+//! Configuration and control of the High and Low Frequency Clock sources.
 
 #[cfg(feature = "9160")]
 use crate::pac::CLOCK_NS as CLOCK;
@@ -9,27 +8,27 @@ use crate::pac::CLOCK;
 
 // ZST Type States
 
-/// Internal/RC Oscillator
+/// Internal/RC Oscillator.
 pub struct Internal;
 
-/// External Crystal Oscillator
+/// External Crystal Oscillator.
 pub struct ExternalOscillator;
 
-/// Low Frequency Clock synthesize from High Frequency Clock
+/// Low Frequency Clock synthesize from High Frequency Clock.
 pub struct LfOscSynthesized;
 
-/// Low Frequency Clock Started
+/// Low Frequency Clock Started.
 pub struct LfOscStarted;
 
-/// Low Frequency Clock Stopped
+/// Low Frequency Clock Stopped.
 pub struct LfOscStopped;
 
-/// High Frequency Clock Frequency (in Hz)
+/// High Frequency Clock Frequency (in Hz).
 pub const HFCLK_FREQ: u32 = 64_000_000;
-/// Low Frequency Clock Frequency (in Hz)
+/// Low Frequency Clock Frequency (in Hz).
 pub const LFCLK_FREQ: u32 = 32_768;
 
-/// A high level abstraction for the CLOCK peripheral
+/// A high level abstraction for the CLOCK peripheral.
 pub struct Clocks<H, L, LSTAT> {
     hfclk: H,
     lfclk: L,
@@ -49,7 +48,7 @@ impl Clocks<Internal, Internal, LfOscStopped> {
 }
 
 impl<H, L, LSTAT> Clocks<H, L, LSTAT> {
-    /// Use an external oscillator as the high frequency clock source
+    /// Use an external oscillator as the high frequency clock source.
     pub fn enable_ext_hfosc(self) -> Clocks<ExternalOscillator, L, LSTAT> {
         self.periph.tasks_hfclkstart.write(|w| unsafe { w.bits(1) });
 
@@ -67,7 +66,7 @@ impl<H, L, LSTAT> Clocks<H, L, LSTAT> {
         }
     }
 
-    /// Use the internal oscillator as the high frequency clock source
+    /// Use the internal oscillator as the high frequency clock source.
     pub fn disable_ext_hfosc(self) -> Clocks<Internal, L, LSTAT> {
         self.periph.tasks_hfclkstop.write(|w| unsafe { w.bits(1) });
         Clocks {
@@ -78,12 +77,12 @@ impl<H, L, LSTAT> Clocks<H, L, LSTAT> {
         }
     }
 
-    /// Start the Low Frequency clock
+    /// Start the Low Frequency clock.
     pub fn start_lfclk(self) -> Clocks<H, L, LfOscStarted> {
         self.periph.tasks_lfclkstart.write(|w| unsafe { w.bits(1) });
 
         // Datasheet says this could take 100us from synth source
-        // 600us from rc source, 0.25s from an external source
+        // 600us from rc source, 0.25s from an external source.
         while self.periph.events_lfclkstarted.read().bits() != 1 {}
         self.periph
             .events_lfclkstarted
@@ -99,15 +98,15 @@ impl<H, L, LSTAT> Clocks<H, L, LSTAT> {
 }
 
 /// Allowable configuration options for the low frequency oscillator when
-/// driven fron an external crystal
+/// driven fron an external crystal.
 pub enum LfOscConfiguration {
     NoExternalNoBypass,
     ExternalNoBypass,
     ExternalAndBypass,
 }
 
 impl<H, L> Clocks<H, L, LfOscStarted> {
-    /// Stop the Low Frequency clock
+    /// Stop the Low Frequency clock.
     pub fn stop_lfclk(self) -> Clocks<H, L, LfOscStopped> {
         self.periph.tasks_lfclkstop.write(|w| unsafe { w.bits(1) });
         Clocks {
@@ -120,7 +119,7 @@ impl<H, L> Clocks<H, L, LfOscStarted> {
 }
 
 impl<H, L> Clocks<H, L, LfOscStopped> {
-    /// Use the internal RC Oscillator for the low frequency clock source
+    /// Use the internal RC Oscillator for the low frequency clock source.
     #[cfg(feature = "51")]
     pub fn set_lfclk_src_rc(self) -> Clocks<H, Internal, LfOscStopped> {
         self.periph.lfclksrc.write(|w| w.src().rc());
@@ -132,7 +131,7 @@ impl<H, L> Clocks<H, L, LfOscStopped> {
         }
     }
 
-    /// Generate the Low Frequency clock from the high frequency clock source
+    /// Generate the Low Frequency clock from the high frequency clock source.
     #[cfg(feature = "51")]
     pub fn set_lfclk_src_synth(self) -> Clocks<H, LfOscSynthesized, LfOscStopped> {
         self.periph.lfclksrc.write(|w| w.src().synth());
@@ -144,7 +143,7 @@ impl<H, L> Clocks<H, L, LfOscStopped> {
         }
     }
 
-    /// Use an external crystal to drive the low frequency clock
+    /// Use an external crystal to drive the low frequency clock.
     #[cfg(feature = "51")]
     pub fn set_lfclk_src_external(self) -> Clocks<H, ExternalOscillator, LfOscStopped> {
         self.periph.lfclksrc.write(move |w| w.src().xtal());
@@ -156,7 +155,7 @@ impl<H, L> Clocks<H, L, LfOscStopped> {
         }
     }
 
-    /// Use the internal RC Oscillator for the low frequency clock source
+    /// Use the internal RC Oscillator for the low frequency clock source.
     #[cfg(not(any(feature = "9160", feature = "51")))]
     pub fn set_lfclk_src_rc(self) -> Clocks<H, Internal, LfOscStopped> {
         self.periph
@@ -170,7 +169,7 @@ impl<H, L> Clocks<H, L, LfOscStopped> {
         }
     }
 
-    /// Generate the Low Frequency clock from the high frequency clock source
+    /// Generate the Low Frequency clock from the high frequency clock source.
     #[cfg(not(any(feature = "9160", feature = "51")))]
     pub fn set_lfclk_src_synth(self) -> Clocks<H, LfOscSynthesized, LfOscStopped> {
         self.periph
@@ -184,7 +183,7 @@ impl<H, L> Clocks<H, L, LfOscStopped> {
         }
     }
 
-    /// Use an external crystal to drive the low frequency clock
+    /// Use an external crystal to drive the low frequency clock.
     #[cfg(not(any(feature = "9160", feature = "51")))]
     pub fn set_lfclk_src_external(
         self,

nrf-hal-common/src/delay.rs

@@ -1,25 +1,25 @@
-//! Delays
+//! Delays.
 use cast::u32;
 use cortex_m::peripheral::syst::SystClkSource;
 use cortex_m::peripheral::SYST;
 
 use crate::clocks::HFCLK_FREQ;
 use crate::hal::blocking::delay::{DelayMs, DelayUs};
 
-/// System timer (SysTick) as a delay provider
+/// System timer (SysTick) as a delay provider.
 pub struct Delay {
     syst: SYST,
 }
 
 impl Delay {
-    /// Configures the system timer (SysTick) as a delay provider
+    /// Configures the system timer (SysTick) as a delay provider.
     pub fn new(mut syst: SYST) -> Self {
         syst.set_clock_source(SystClkSource::Core);
 
         Delay { syst }
     }
 
-    /// Releases the system timer (SysTick) resource
+    /// Releases the system timer (SysTick) resource.
     pub fn free(self) -> SYST {
         self.syst
     }

nrf-hal-common/src/ecb.rs

@@ -24,7 +24,7 @@ impl Ecb {
         regs.intenclr
             .write(|w| w.endecb().clear().errorecb().clear());
 
-        // NOTE(unsafe) 1 is a valid pattern to write to this register
+        // NOTE(unsafe) 1 is a valid pattern to write to this register.
         regs.tasks_stopecb.write(|w| unsafe { w.bits(1) });
         Self { regs }
     }
@@ -68,12 +68,12 @@ impl Ecb {
             cipher_text: [0; 16],
         };
 
-        // NOTE(unsafe) Any 32bits pattern is safe to write to this register
+        // NOTE(unsafe) Any 32bits pattern is safe to write to this register.
         self.regs
             .ecbdataptr
             .write(|w| unsafe { w.bits(&mut buf as *mut _ as u32) });
 
-        // Clear all events
+        // Clear all events.
         self.regs.events_endecb.reset();
         self.regs.events_errorecb.reset();
 
@@ -90,7 +90,7 @@ impl Ecb {
         compiler_fence(Ordering::Acquire);
 
         if self.regs.events_errorecb.read().bits() == 1 {
-            // It's ok to return here, the events will be cleared before the next encryption
+            // It's ok to return here, the events will be cleared before the next encryption.
             return Err(EncryptionError {});
         }
         Ok(buf.cipher_text)

nrf-hal-common/src/gpio.rs

@@ -1,28 +1,28 @@
 use core::marker::PhantomData;
 
-/// Input mode (type state)
+/// Input mode (type state).
 pub struct Input<MODE> {
     _mode: PhantomData<MODE>,
 }
 
-/// Floating input (type state)
+/// Floating input (type state).
 pub struct Floating;
-/// Pulled down input (type state)
+/// Pulled down input (type state).
 pub struct PullDown;
-/// Pulled up input (type state)
+/// Pulled up input (type state).
 pub struct PullUp;
 
-/// Output mode (type state)
+/// Output mode (type state).
 pub struct Output<MODE> {
     _mode: PhantomData<MODE>,
 }
 
-/// Push pull output (type state)
+/// Push pull output (type state).
 pub struct PushPull;
-/// Open drain output (type state)
+/// Open drain output (type state).
 pub struct OpenDrain;
 
-/// Represents a digital input or output level
+/// Represents a digital input or output level.
 pub enum Level {
     Low,
     High,
@@ -175,7 +175,7 @@ impl<MODE> Pin<MODE> {
         }
     }
 
-    /// Convert the pin to be a push-pull output with normal drive
+    /// Convert the pin to be a push-pull output with normal drive.
     pub fn into_push_pull_output(self, initial_output: Level) -> Pin<Output<PushPull>> {
         let mut pin = Pin {
             _mode: PhantomData,
@@ -199,10 +199,10 @@ impl<MODE> Pin<MODE> {
         pin
     }
 
-    /// Convert the pin to be an open-drain output
+    /// Convert the pin to be an open-drain output.
     ///
-    /// This method currently does not support configuring an
-    /// internal pull-up or pull-down resistor.
+    /// This method currently does not support configuring an internal pull-up or pull-down
+    /// resistor.
     pub fn into_open_drain_output(
         self,
         config: OpenDrainConfig,
@@ -218,8 +218,7 @@ impl<MODE> Pin<MODE> {
             Level::High => pin.set_high().unwrap(),
         }
 
-        // This is safe, as we restrict our access to the dedicated
-        // register for this pin.
+        // This is safe, as we restrict our access to the dedicated register for this pin.
         let pin_cnf = &self.block().pin_cnf[self.pin() as usize];
         pin_cnf.write(|w| {
             w.dir().output();
@@ -249,7 +248,7 @@ impl<MODE> InputPin for Pin<Input<MODE>> {
 impl<MODE> OutputPin for Pin<Output<MODE>> {
     type Error = Void;
 
-    /// Set the output as high
+    /// Set the output as high.
     fn set_high(&mut self) -> Result<(), Self::Error> {
         // NOTE(unsafe) atomic write to a stateless register - TODO(AJM) verify?
         // TODO - I wish I could do something like `.pins$i()`...
@@ -259,7 +258,7 @@ impl<MODE> OutputPin for Pin<Output<MODE>> {
         Ok(())
     }
 
-    /// Set the output as low
+    /// Set the output as low.
     fn set_low(&mut self) -> Result<(), Self::Error> {
         // NOTE(unsafe) atomic write to a stateless register - TODO(AJM) verify?
         // TODO - I wish I could do something like `.pins$i()`...
@@ -284,7 +283,7 @@ impl<MODE> StatefulOutputPin for Pin<Output<MODE>> {
     }
 }
 
-/// Pin configuration for open-drain mode
+/// Pin configuration for open-drain mode.
 pub enum OpenDrainConfig {
     Disconnect0Standard1,
     Disconnect0HighDrive1,