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This PR vendors AIEVec and XLLVM (including ops/types/attrs etc.). Importantly, we only vendor the components related to translation to llvm ir (no codegen/optimization/etc). The reason for this is the goal of this sprint is to support chess via the llvm ir path i.e., we will add support for chess aie2 intrinsics here instead of mlir-aie.
Note we greatly reduce the number of supported aievec ops down to
matmul
,shuffle
,srs
,ups
,cast
.