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remove target model
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@makslevental
makslevental committed Jun 18, 2024
1 parent 8d426dc commit 95be436
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Showing 5 changed files with 100 additions and 38 deletions.
7 changes: 4 additions & 3 deletions compiler/plugins/target/AMD-AIE/aie/AIEPass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@
#include "aie/Dialect/AIE/IR/AIEDialect.h"
#include "aie/Dialect/AIEX/IR/AIEXDialect.h"
#include "d_ary_heap.h"
#include "iree-amd-aie/runtime/iree_aie_runtime.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/Debug.h"
Expand Down Expand Up @@ -213,7 +214,7 @@ void xilinx::AIE::registerAIEAssignBufferAddressesBasic() {
#define ODD_BD_ID_START 24

struct BdIdGenerator {
BdIdGenerator(int col, int row, const AIETargetModel &targetModel)
BdIdGenerator(int col, int row, AMDAIENPUTargetModel targetModel)
: col(col), row(row), isMemTile(targetModel.isMemTile(col, row)) {}

int32_t nextBdId(int channelIndex) {
Expand Down Expand Up @@ -244,7 +245,7 @@ struct AIEAssignBufferDescriptorIDsPass
AIEAssignBufferDescriptorIDsPass> {
void runOnOperation() override {
DeviceOp targetOp = getOperation();
const AIETargetModel &targetModel = targetOp.getTargetModel();
AMDAIENPUTargetModel targetModel = targetOp.getTargetModel();

auto memOps = llvm::to_vector_of<TileElement>(targetOp.getOps<MemOp>());
llvm::append_range(memOps, targetOp.getOps<MemTileDMAOp>());
Expand Down Expand Up @@ -2876,7 +2877,7 @@ ShimMuxOp DynamicTileAnalysis::getShimMux(OpBuilder &builder, int col) {
}

void Pathfinder::initialize(int maxCol, int maxRow,
const AIETargetModel &targetModel) {
AMDAIENPUTargetModel targetModel) {
// make grid of switchboxes
int id = 0;
for (int row = 0; row <= maxRow; row++) {
Expand Down
54 changes: 27 additions & 27 deletions compiler/plugins/target/AMD-AIE/aie/AIEPathFinder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -11,17 +11,16 @@
#ifndef AIE_PATHFINDER_H
#define AIE_PATHFINDER_H

#include "aie/Dialect/AIE/IR/AIEDialect.h"
#include "aie/Dialect/AIE/IR/AIETargetModel.h"

#include "llvm/ADT/DirectedGraph.h"
#include "llvm/ADT/GraphTraits.h"

#include <algorithm>
#include <iostream>
#include <list>
#include <set>

#include "aie/Dialect/AIE/IR/AIEDialect.h"
#include "iree-amd-aie/runtime/iree_aie_runtime.h"
#include "llvm/ADT/DirectedGraph.h"
#include "llvm/ADT/GraphTraits.h"

namespace xilinx::AIE {

using Switchbox = struct Switchbox : TileID {
Expand Down Expand Up @@ -60,11 +59,11 @@ using Channel = struct Channel {
Switchbox &src;
Switchbox &target;
WireBundle bundle;
int maxCapacity = 0; // maximum number of routing resources
double demand = 0.0; // indicates how many flows want to use this Channel
int usedCapacity = 0; // how many flows are actually using this Channel
std::set<int> fixedCapacity; // channels not available to the algorithm
int overCapacityCount = 0; // history of Channel being over capacity
int maxCapacity = 0; // maximum number of routing resources
double demand = 0.0; // indicates how many flows want to use this Channel
int usedCapacity = 0; // how many flows are actually using this Channel
std::set<int> fixedCapacity; // channels not available to the algorithm
int overCapacityCount = 0; // history of Channel being over capacity
};

struct SwitchboxNode;
Expand All @@ -87,7 +86,8 @@ using ChannelEdge = struct ChannelEdge : ChannelEdgeBase, Channel {
explicit ChannelEdge(SwitchboxNode &target) = delete;
ChannelEdge(SwitchboxNode &src, SwitchboxNode &target, WireBundle bundle,
int maxCapacity)
: ChannelEdgeBase(target), Channel(src, target, bundle, maxCapacity),
: ChannelEdgeBase(target),
Channel(src, target, bundle, maxCapacity),
src(src) {}

// This class isn't designed to copied or moved.
Expand All @@ -98,7 +98,7 @@ using ChannelEdge = struct ChannelEdge : ChannelEdgeBase, Channel {
};

class SwitchboxGraph : public SwitchboxGraphBase {
public:
public:
SwitchboxGraph() = default;
~SwitchboxGraph() = default;
};
Expand Down Expand Up @@ -187,31 +187,31 @@ using FlowNode = struct FlowNode {
};

class Router {
public:
public:
Router() = default;
// This has to go first so it can serve as a key function.
// https://lld.llvm.org/missingkeyfunction
virtual ~Router() = default;
virtual void initialize(int maxCol, int maxRow,
const AIETargetModel &targetModel) = 0;
AMDAIENPUTargetModel targetModel) = 0;
virtual void addFlow(TileID srcCoords, Port srcPort, TileID dstCoords,
Port dstPort) = 0;
virtual bool addFixedConnection(ConnectOp connectOp) = 0;
virtual std::optional<std::map<PathEndPoint, SwitchSettings>>
findPaths(int maxIterations) = 0;
virtual std::optional<std::map<PathEndPoint, SwitchSettings>> findPaths(
int maxIterations) = 0;
virtual Switchbox *getSwitchbox(TileID coords) = 0;
};

class Pathfinder : public Router {
public:
public:
Pathfinder() = default;
void initialize(int maxCol, int maxRow,
const AIETargetModel &targetModel) override;
AMDAIENPUTargetModel targetModel) override;
void addFlow(TileID srcCoords, Port srcPort, TileID dstCoords,
Port dstPort) override;
bool addFixedConnection(ConnectOp connectOp) override;
std::optional<std::map<PathEndPoint, SwitchSettings>>
findPaths(int maxIterations) override;
std::optional<std::map<PathEndPoint, SwitchSettings>> findPaths(
int maxIterations) override;

Switchbox *getSwitchbox(TileID coords) override {
auto *sb = std::find_if(graph.begin(), graph.end(), [&](SwitchboxNode *sb) {
Expand All @@ -221,7 +221,7 @@ class Pathfinder : public Router {
return *sb;
}

private:
private:
SwitchboxGraph graph;
std::vector<FlowNode> flows;
std::map<TileID, SwitchboxNode> grid;
Expand All @@ -235,7 +235,7 @@ class Pathfinder : public Router {
// Detailed routing is received as SwitchboxSettings
// It then converts these settings to MLIR operations
class DynamicTileAnalysis {
public:
public:
int maxCol, maxRow;
std::shared_ptr<Router> pathfinder;
std::map<PathEndPoint, SwitchSettings> flowSolutions;
Expand All @@ -246,7 +246,7 @@ class DynamicTileAnalysis {
llvm::DenseMap<TileID, ShimMuxOp> coordToShimMux;
llvm::DenseMap<int, PLIOOp> coordToPLIO;

const int maxIterations = 1000; // how long until declared unroutable
const int maxIterations = 1000; // how long until declared unroutable

DynamicTileAnalysis() : pathfinder(std::make_shared<Pathfinder>()) {}
DynamicTileAnalysis(std::shared_ptr<Router> p) : pathfinder(std::move(p)) {}
Expand All @@ -263,7 +263,7 @@ class DynamicTileAnalysis {
ShimMuxOp getShimMux(mlir::OpBuilder &builder, int col);
};

} // namespace xilinx::AIE
} // namespace xilinx::AIE

// For some mysterious reason, the only way to get the priorityQueue(cmp)
// comparison in dijkstraShortestPaths to work correctly is to define
Expand All @@ -281,7 +281,7 @@ struct less<xilinx::AIE::Switchbox *> {
return *a < *b;
}
};
} // namespace std
} // namespace std

namespace llvm {

Expand Down Expand Up @@ -342,7 +342,7 @@ inline raw_ostream &operator<<(raw_ostream &os,
return os;
}

} // namespace llvm
} // namespace llvm

template <>
struct std::hash<xilinx::AIE::Switchbox> {
Expand Down
14 changes: 7 additions & 7 deletions compiler/plugins/target/AMD-AIE/aie/AIETargetCDODirect.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,8 @@
//===----------------------------------------------------------------------===//

#include "AIETargets.h"
#include "aie/Dialect/AIE/IR/AIETargetModel.h"
#include "iree-amd-aie/runtime/iree_aie_runtime.h"

extern "C" {
#include "cdo-driver/cdo_driver.h"
}
Expand Down Expand Up @@ -189,7 +190,7 @@ auto ps = std::filesystem::path::preferred_separator;
namespace xilinx::AIE {

LogicalResult configureLocksInBdBlock(XAie_DmaDesc &dmaTileBd, Block &block,
const AIETargetModel &targetModel,
AMDAIENPUTargetModel targetModel,
XAie_LocType &tileLoc) {
LLVM_DEBUG(llvm::dbgs() << "\nstart configuring bds\n");
std::optional<int> acqValue, relValue, acqLockId, relLockId;
Expand Down Expand Up @@ -235,8 +236,7 @@ LogicalResult configureLocksInBdBlock(XAie_DmaDesc &dmaTileBd, Block &block,
}

LogicalResult configureBdInBlock(XAie_DevInst &devInst, XAie_DmaDesc &dmaTileBd,
Block &block,
const AIETargetModel &targetModel,
Block &block, AMDAIENPUTargetModel targetModel,
XAie_LocType &tileLoc, int bdId,
std::optional<int> nextBdId) {
std::optional<int> packetType;
Expand Down Expand Up @@ -360,7 +360,7 @@ LogicalResult pushToBdQueueAndEnable(XAie_DevInst &devInst, Operation &op,

LogicalResult configureLocksAndBd(XAie_DevInst &devInst, Block &block,
XAie_LocType tileLoc,
const AIETargetModel &targetModel) {
AMDAIENPUTargetModel targetModel) {
DMABDOp bd = *block.getOps<DMABDOp>().begin();
assert(bd.getBdId().has_value() &&
"DMABDOp must have assigned bd_id; did you forget to run "
Expand All @@ -382,7 +382,7 @@ struct AIEControl {
XAie_DevInst devInst;

AIEControl(size_t partitionStartCol, bool aieSim, bool xaieDebug,
const AIETargetModel &tm) {
AMDAIENPUTargetModel tm) {
size_t partitionNumCols = tm.columns();
size_t deviceRows = tm.rows();
size_t deviceCols = tm.columns() + partitionStartCol;
Expand Down Expand Up @@ -489,7 +489,7 @@ struct AIEControl {
<< "lock op missing either id or init" << lockOp << "\n");
});

const AIETargetModel &targetModel = targetOp.getTargetModel();
AMDAIENPUTargetModel targetModel = targetOp.getTargetModel();

auto memOps = llvm::to_vector_of<TileElement>(targetOp.getOps<MemOp>());
llvm::append_range(memOps, targetOp.getOps<MemTileDMAOp>());
Expand Down
2 changes: 1 addition & 1 deletion compiler/plugins/target/AMD-AIE/aie/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,6 @@ iree_cc_library(
AIEDialectIR
SRCS
${IREE_MLIR_AIE_SOURCE_DIR}/lib/Dialect/AIE/IR/AIEDialect.cpp
${IREE_MLIR_AIE_SOURCE_DIR}/lib/Dialect/AIE/IR/AIETargetModel.cpp
DEPS
::defs
::AIEAttrsGen
Expand Down Expand Up @@ -322,6 +321,7 @@ iree_cc_library(
::AIETransformPassHeaders
::AIEXDialectIR
::AIEXTransformPassHeaders
iree-amd-aie::runtime::iree_aie_runtime_static
)

###############################################################################
Expand Down
61 changes: 61 additions & 0 deletions runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,8 @@
#ifndef IREE_AIE_RUNTIME_H
#define IREE_AIE_RUNTIME_H

#include <optional>

#ifdef _WIN32
#ifndef IREE_AIE_RUNTIME_EXPORT
#ifdef iree_aie_runtime_EXPORTS
Expand Down Expand Up @@ -34,4 +36,63 @@ void setEndianness(bool endianness);
void configureHeader();
}

struct AMDAIENPUTargetModel {
int rows() { return 6; /* 1 Shim row, 1 memtile row, and 4 Core rows. */ }
int columns() { return 5; }

bool isCoreTile(int col, int row) { return row > 1; }

bool isMemTile(int col, int row) { return row == 1; }

uint32_t getNumLocks(int col, int row) {
return isMemTile(col, row) ? 64 : 16;
}

bool isShimNOCTile(int col, int row) { return row == 0 && col > 0; }

bool isShimPLTile(int col, int row) {
// This isn't useful because it's not connected to anything.
return row == 0 && col == 0;
}

uint32_t getNumMemTileRows() { return 1; }

std::optional<XAie_LocType> getMemWest(XAie_LocType src);
std::optional<XAie_LocType> getMemEast(XAie_LocType src);
std::optional<XAie_LocType> getMemNorth(XAie_LocType src);
std::optional<XAie_LocType> getMemSouth(XAie_LocType src);

bool isMemWest(int srcCol, int srcRow, int dstCol, int dstRow);
bool isMemEast(int srcCol, int srcRow, int dstCol, int dstRow);
bool isMemNorth(int srcCol, int srcRow, int dstCol, int dstRow);
bool isMemSouth(int srcCol, int srcRow, int dstCol, int dstRow);

bool isLegalMemAffinity(int coreCol, int coreRow, int memCol, int memRow);

static uint32_t getMemInternalBaseAddress() {
return getMemEastBaseAddress();
}

static uint32_t getMemSouthBaseAddress() { return 0x00040000; }
static uint32_t getMemWestBaseAddress() { return 0x00050000; }
static uint32_t getMemNorthBaseAddress() { return 0x00060000; }
static uint32_t getMemEastBaseAddress() { return 0x00070000; }
static uint32_t getLocalMemorySize() { return 0x00010000; }

uint32_t getNumBDs(int col, int row) { return isMemTile(col, row) ? 48 : 16; }

uint32_t getMemTileSize() { return 0x00080000; }

uint32_t getNumDestSwitchboxConnections(int col, int row,
StrmSwPortType bundle);
uint32_t getNumSourceSwitchboxConnections(int col, int row,
StrmSwPortType bundle);
uint32_t getNumDestShimMuxConnections(int col, int row,
StrmSwPortType bundle);
uint32_t getNumSourceShimMuxConnections(int col, int row,
StrmSwPortType bundle);
bool isLegalMemtileConnection(StrmSwPortType srcBundle, int srcChan,
StrmSwPortType dstBundle, int dstChan);
};

#endif // IREE_AIE_RUNTIME_H

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