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CR Fixes #1
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@nmostafa
nmostafa committed Mar 1, 2016
1 parent 0e09b9f commit a811709
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Showing 3 changed files with 69 additions and 126 deletions.
146 changes: 44 additions & 102 deletions lib/Backend/IRBuilderAsmJs.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -885,51 +885,7 @@ IRBuilderAsmJs::BuildImplicitArgIns()
{
// SIMD_JS
IRType argType;
if (varType.which() == Js::AsmJsVarType::Which::Float32x4)
{
argType = TySimd128F4;
}
else if (varType.which() == Js::AsmJsVarType::Which::Int32x4)
{
argType = TySimd128I4;
}
else if (varType.which() == Js::AsmJsVarType::Which::Bool32x4)
{
argType = TySimd128B4;
}
else if (varType.which() == Js::AsmJsVarType::Which::Bool16x8)
{
argType = TySimd128B8;
}
else if (varType.which() == Js::AsmJsVarType::Which::Bool8x16)
{
argType = TySimd128B16;
}
else if (varType.which() == Js::AsmJsVarType::Which::Float64x2)
{
argType = TySimd128D2;
}
else if (varType.which() == Js::AsmJsVarType::Which::Int16x8)
{
argType = TySimd128I8;
}
else if (varType.which() == Js::AsmJsVarType::Which::Int8x16)
{
argType = TySimd128I16;
}
else if (varType.which() == Js::AsmJsVarType::Which::Uint32x4)
{
argType = TySimd128U4;
}
else if (varType.which() == Js::AsmJsVarType::Which::Uint16x8)
{
argType = TySimd128U8;
}
else
{
Assert(varType.which() == Js::AsmJsVarType::Which::Uint8x16);
argType = TySimd128U16;
}
GetSimdTypesFromAsmType((Js::AsmJsType::Which)varType.which(), &argType);

symSrc = StackSym::NewParamSlotSym(i, m_func, argType);
m_func->SetArgOffset(symSrc, offset);
Expand Down Expand Up @@ -1067,64 +1023,16 @@ IRBuilderAsmJs::BuildEmpty(Js::OpCodeAsmJs newOpcode, uint32 offset)
retSlot = GetRegSlotFromVarReg(0);
regOpnd = BuildDstOpnd(retSlot, TyVar);
break;

case Js::AsmJsRetType::Which::Float32x4:
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, TySimd128F4);
regOpnd->SetValueType(ValueType::GetSimd128(ObjectType::Simd128Float32x4));
break;
case Js::AsmJsRetType::Which::Int32x4:
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, TySimd128I4);
regOpnd->SetValueType(ValueType::GetSimd128(ObjectType::Simd128Int32x4));
break;
case Js::AsmJsRetType::Which::Bool32x4:
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, TySimd128B4);
regOpnd->SetValueType(ValueType::GetSimd128(ObjectType::Simd128Bool32x4));
break;
case Js::AsmJsRetType::Which::Bool16x8:
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, TySimd128B8);
regOpnd->SetValueType(ValueType::GetSimd128(ObjectType::Simd128Bool16x8));
break;
case Js::AsmJsRetType::Which::Bool8x16:
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, TySimd128B16);
regOpnd->SetValueType(ValueType::GetSimd128(ObjectType::Simd128Bool8x16));
break;
case Js::AsmJsRetType::Which::Float64x2:
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, TySimd128D2);
regOpnd->SetValueType(ValueType::GetSimd128(ObjectType::Simd128Float64x2));
break;
case Js::AsmJsRetType::Which::Int16x8:
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, TySimd128I8);
regOpnd->SetValueType(ValueType::GetSimd128(ObjectType::Simd128Int16x8));
break;
case Js::AsmJsRetType::Which::Int8x16:
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, TySimd128I16);
regOpnd->SetValueType(ValueType::GetSimd128(ObjectType::Simd128Int8x16));
break;
case Js::AsmJsRetType::Which::Uint32x4:
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, TySimd128U4);
regOpnd->SetValueType(ValueType::GetSimd128(ObjectType::Simd128Int16x8));
break;
case Js::AsmJsRetType::Which::Uint16x8:
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, TySimd128U8);
regOpnd->SetValueType(ValueType::GetSimd128(ObjectType::Simd128Uint16x8));
break;
case Js::AsmJsRetType::Which::Uint8x16:
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, TySimd128U16);
regOpnd->SetValueType(ValueType::GetSimd128(ObjectType::Simd128Uint8x16));
break;
default:
Assume(UNREACHED);
{
IRType irType;
ValueType vType;
GetSimdTypesFromAsmType(m_asmFuncInfo->GetReturnType().toType().GetWhich(), &irType, &vType);
retSlot = GetRegSlotFromSimd128Reg(0);
regOpnd = BuildDstOpnd(retSlot, irType);
regOpnd->SetValueType(vType);
}

}
instr->SetSrc1(regOpnd);
AddInstr(instr, offset);
Expand Down Expand Up @@ -3471,6 +3379,40 @@ inline Js::OpCode IRBuilderAsmJs::GetSimdOpcode(Js::OpCodeAsmJs asmjsOpcode)
return opcode;
}

void IRBuilderAsmJs::GetSimdTypesFromAsmType(Js::AsmJsType::Which asmType, IRType *pIRType, ValueType *pValueType /* = nullptr */)
{
IRType irType = IRType::TyVar;
ValueType vType = ValueType::Uninitialized;

#define SIMD_TYPE_CHECK(type1, type2, type3) \
case Js::AsmJsType::Which::##type1: \
irType = type2; \
vType = ValueType::GetSimd128(ObjectType::##type3); \
break;

switch (asmType)
{
SIMD_TYPE_CHECK(Float32x4, TySimd128F4, Simd128Float32x4)
SIMD_TYPE_CHECK(Int32x4, TySimd128I4, Simd128Int32x4 )
SIMD_TYPE_CHECK(Int16x8, TySimd128I8, Simd128Int16x8 )
SIMD_TYPE_CHECK(Int8x16, TySimd128I16, Simd128Int8x16 )
SIMD_TYPE_CHECK(Uint32x4, TySimd128U4, Simd128Uint32x4 )
SIMD_TYPE_CHECK(Uint16x8, TySimd128U8, Simd128Uint16x8 )
SIMD_TYPE_CHECK(Uint8x16, TySimd128U16, Simd128Uint8x16 )
SIMD_TYPE_CHECK(Bool32x4, TySimd128B4, Simd128Bool32x4 )
SIMD_TYPE_CHECK(Bool16x8, TySimd128B8, Simd128Bool16x8 )
SIMD_TYPE_CHECK(Bool8x16, TySimd128B16, Simd128Bool8x16 )
default:
Assert(UNREACHED);
}
*pIRType = irType;
if (pValueType)
{
*pValueType = vType;
}
#undef SIMD_TYPE_CHECK
}


// !!NOTE: Always build the src opnds first, before dst. So we record the use of any temps before assigning new symId for the dst temp.

Expand Down
1 change: 1 addition & 0 deletions lib/Backend/IRBuilderAsmJs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -84,6 +84,7 @@ class IRBuilderAsmJs
Js::RegSlot GetRegSlotFromDoubleReg(Js::RegSlot srcDoubleReg);
Js::RegSlot GetRegSlotFromVarReg(Js::RegSlot srcVarReg);
Js::OpCode GetSimdOpcode(Js::OpCodeAsmJs asmjsOpcode);
void GetSimdTypesFromAsmType(Js::AsmJsType::Which asmType, IRType *pIRType, ValueType *pValueType = nullptr);
Js::RegSlot GetRegSlotFromSimd128Reg(Js::RegSlot srcSimd128Reg);
IR::Instr * AddExtendedArg(IR::RegOpnd *src1, IR::RegOpnd *src2, uint32 offset);
BOOL RegIsSimd128Var(Js::RegSlot reg);
Expand Down
48 changes: 24 additions & 24 deletions lib/Backend/LowerMDSharedSimd128.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1225,24 +1225,24 @@ IR::Instr* LowererMD::Simd128LowerShift(IR::Instr *instr)

switch (instr->m_opcode)
{
case Js::OpCode::Simd128_ShLtByScalar_I4: // 66 0F 72 /6 ib (PSLLD) int32x4
case Js::OpCode::Simd128_ShLtByScalar_I4:
case Js::OpCode::Simd128_ShLtByScalar_U4: // same as int32x4.ShiftLeftScalar
opcode = Js::OpCode::PSLLD;
break;
case Js::OpCode::Simd128_ShRtByScalar_I4: // 66 0F 72 /4 ib (PSRAD) int32x4
case Js::OpCode::Simd128_ShRtByScalar_I4:
opcode = Js::OpCode::PSRAD;
break;
case Js::OpCode::Simd128_ShLtByScalar_I8: // 66 0F 71 /6 ib (PSLLW) int16x8
case Js::OpCode::Simd128_ShLtByScalar_I8:
case Js::OpCode::Simd128_ShLtByScalar_U8: // same as int16x8.ShiftLeftScalar
opcode = Js::OpCode::PSLLW;
break;
case Js::OpCode::Simd128_ShRtByScalar_I8: // 66 0F 71 /4 ib (PSRAW) int16x8
case Js::OpCode::Simd128_ShRtByScalar_I8:
opcode = Js::OpCode::PSRAW;
break;
case Js::OpCode::Simd128_ShRtByScalar_U4: // 66 0F 72 /2 ib (PSRLD) uint32x4
case Js::OpCode::Simd128_ShRtByScalar_U4:
opcode = Js::OpCode::PSRLD;
break;
case Js::OpCode::Simd128_ShRtByScalar_U8: // 66 0F 71 /2 ib (PSRLW) uint16x8
case Js::OpCode::Simd128_ShRtByScalar_U8:
opcode = Js::OpCode::PSRLW;
break;
case Js::OpCode::Simd128_ShLtByScalar_I16: // composite, int8x16.ShiftLeftScalar
Expand Down Expand Up @@ -2418,12 +2418,12 @@ IR::Instr* LowererMD::Simd128LowerAnyTrue(IR::Instr* instr)
IR::Opnd* src1 = instr->GetSrc1();
Assert(dst->IsRegOpnd() && dst->IsInt32());
Assert(src1->IsRegOpnd() && src1->IsSimd128());
// pmovmskb dst, src1 (66 0F D7 /r PMOVMSKB r32, xmm)
// pmovmskb dst, src1
// neg dst
// sbb dst, dst
// neg dst

// pmovmskb dst, src1 (66 0F D7 /r PMOVMSKB r32, xmm)
// pmovmskb dst, src1
pInstr = IR::Instr::New(Js::OpCode::PMOVMSKB, dst, src1, m_func);
instr->InsertBefore(pInstr);
Legalize(pInstr);
Expand Down Expand Up @@ -2460,7 +2460,7 @@ IR::Instr* LowererMD::Simd128LowerAllTrue(IR::Instr* instr)
Assert(dst->IsRegOpnd() && dst->IsInt32());
Assert(src1->IsRegOpnd() && src1->IsSimd128());
// mov dst, 0
// pmovmskb reg, src1 (66 0F D7 /r PMOVMSKB r32, xmm)
// pmovmskb reg, src1
// cmp reg, 0FFFFh
// sete dst, (al)

Expand All @@ -2472,7 +2472,7 @@ IR::Instr* LowererMD::Simd128LowerAllTrue(IR::Instr* instr)
instr->InsertBefore(pInstr);
Legalize(pInstr);

// pmovmskb reg, src1 (66 0F D7 /r PMOVMSKB r32, xmm)
// pmovmskb reg, src1
pInstr = IR::Instr::New(Js::OpCode::PMOVMSKB, reg, src1, m_func);
instr->InsertBefore(pInstr);

Expand Down Expand Up @@ -2652,7 +2652,7 @@ IR::Instr* LowererMD::Simd128LowerUint32x4FromFloat32x4(IR::Instr *instr)
Legalize(newInstr);

// check if any value is out of range (i.e. >= 2^31, meaning originally >= 2^32 before value adjustment)
// CMPEQPS tmp, dst, [X86_NEG_MASK]
// PCMPEQD tmp, dst, [X86_NEG_MASK]
// MOVMSKPS mask, tmp
// CMP mask, 0
// JNE $throwLabel
Expand Down Expand Up @@ -3293,16 +3293,16 @@ void LowererMD::Simd128InitOpcodeMap()
SET_SIMDOPCODE(Simd128_Add_I8 , PADDW);
SET_SIMDOPCODE(Simd128_Sub_I8 , PSUBW);
SET_SIMDOPCODE(Simd128_Mul_I8 , PMULLW);
SET_SIMDOPCODE(Simd128_Min_I8 , PMINSW); // 66 0F EA /r PMINSW xmm1, xmm2/m128
SET_SIMDOPCODE(Simd128_Max_I8 , PMAXSW); // 66 0F EE /r PMAXSW xmm1, xmm2/m128
SET_SIMDOPCODE(Simd128_Min_I8 , PMINSW);
SET_SIMDOPCODE(Simd128_Max_I8 , PMAXSW);
SET_SIMDOPCODE(Simd128_Eq_I8 , PCMPEQW);
SET_SIMDOPCODE(Simd128_Lt_I8 , PCMPGTW); // (swap srcs)
SET_SIMDOPCODE(Simd128_Gt_I8 , PCMPGTW);
SET_SIMDOPCODE(Simd128_AddSaturate_I8 , PADDSW); // 66 0F ED paddsw xmm0,xmm1/m128
SET_SIMDOPCODE(Simd128_SubSaturate_I8 , PSUBSW); // 66 0F E9 psubsw xmm0,xmm1/m128
SET_SIMDOPCODE(Simd128_AddSaturate_I8 , PADDSW);
SET_SIMDOPCODE(Simd128_SubSaturate_I8 , PSUBSW);

SET_SIMDOPCODE(Simd128_AddSaturate_I16 , PADDSB); // 66 0F EC paddsb xmm0,xmm1/m128
SET_SIMDOPCODE(Simd128_SubSaturate_I16 , PSUBSB); // 66 0F E8 psubsb xmm0,xmm1/m128
SET_SIMDOPCODE(Simd128_AddSaturate_I16 , PADDSB);
SET_SIMDOPCODE(Simd128_SubSaturate_I16 , PSUBSB);

SET_SIMDOPCODE(Simd128_And_U4 , PAND);
SET_SIMDOPCODE(Simd128_Or_U4 , POR);
Expand All @@ -3319,21 +3319,21 @@ void LowererMD::Simd128InitOpcodeMap()
SET_SIMDOPCODE(Simd128_Add_U8 , PADDW);
SET_SIMDOPCODE(Simd128_Sub_U8 , PSUBW);
SET_SIMDOPCODE(Simd128_Mul_U8 , PMULLW);
SET_SIMDOPCODE(Simd128_Eq_U8 , PCMPEQB); // same as int16X8.equal , 66 0F 74 /r PCMPEQB xmm1, xmm2/m128
SET_SIMDOPCODE(Simd128_AddSaturate_U8 , PADDUSW); // 66 0F DD paddusw xmm0,xmm1/m128
SET_SIMDOPCODE(Simd128_SubSaturate_U8 , PSUBUSW); // 66 0F D9 psubusw xmm0,xmm1/m128
SET_SIMDOPCODE(Simd128_Eq_U8 , PCMPEQB); // same as int16X8.equal
SET_SIMDOPCODE(Simd128_AddSaturate_U8 , PADDUSW);
SET_SIMDOPCODE(Simd128_SubSaturate_U8 , PSUBUSW);

SET_SIMDOPCODE(Simd128_And_U16 , PAND);
SET_SIMDOPCODE(Simd128_Or_U16 , POR);
SET_SIMDOPCODE(Simd128_Xor_U16 , XORPS);
SET_SIMDOPCODE(Simd128_Not_U16 , XORPS);
SET_SIMDOPCODE(Simd128_Add_U16 , PADDB);
SET_SIMDOPCODE(Simd128_Sub_U16 , PSUBB);
SET_SIMDOPCODE(Simd128_Min_U16 , PMINUB); // 66 0F DA /r PMINUB xmm1, xmm2/m128
SET_SIMDOPCODE(Simd128_Max_U16 , PMAXUB); // 66 0F DE /r PMAXUB xmm1, xmm2/m128
SET_SIMDOPCODE(Simd128_Min_U16 , PMINUB);
SET_SIMDOPCODE(Simd128_Max_U16 , PMAXUB);
SET_SIMDOPCODE(Simd128_Eq_U16 , PCMPEQB); // same as int16x8.equal
SET_SIMDOPCODE(Simd128_AddSaturate_U16 , PADDUSB); // 66 0F DC paddusb xmm0,xmm1/m128
SET_SIMDOPCODE(Simd128_SubSaturate_U16 , PSUBUSB); // 66 0F D8 psubusb xmm0,xmm1/m128
SET_SIMDOPCODE(Simd128_AddSaturate_U16 , PADDUSB);
SET_SIMDOPCODE(Simd128_SubSaturate_U16 , PSUBUSB);

SET_SIMDOPCODE(Simd128_And_B4 , PAND);
SET_SIMDOPCODE(Simd128_Or_B4 , POR);
Expand Down

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