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[VTA][Chisel] End-to-end Inference with Chisel VTA (apache#4574)
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* [VTA][Chisel] End-to-end Inference with Chisel VTA

* Update TensorAlu.scala
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liangfu authored and zhiics committed Jan 11, 2020
1 parent 51de79a commit 313bd46
Showing 1 changed file with 2 additions and 1 deletion.
3 changes: 2 additions & 1 deletion vta/hardware/chisel/src/main/scala/core/TensorAlu.scala
Original file line number Diff line number Diff line change
Expand Up @@ -230,7 +230,8 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
tensorImm.data.valid := state === sReadTensorB
tensorImm.data.bits.foreach { b =>
b.foreach { c =>
c := dec.alu_imm
c := Mux(dec.alu_imm(C_ALU_IMM_BITS - 1),
Cat(-1.S((aluBits - C_ALU_IMM_BITS).W), dec.alu_imm), dec.alu_imm)
}
}

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